Lateral Insulated Gate Bipolar Transistor Research Articles

A New Low Turn-Off Loss SOI Lateral Insulated Gate Bipolar Transistor With Buried Variation of Lateral Doping Layer

In this paper, we propose a new low turn-off loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with buried variation of lateral doping (VLD) layer. The proposed device features a VLD layer inserted in the drift region, which increases the doping dose ( Q ) and gradient ( G ) compared with Uniform P-buried (UPB) SOI LIGBT. The larger capacitance effect induced by lager Q and faster depletion leads to the lower rising anode voltage and reduced storage charge in the drift region. Therefore, a considerable low turn-off loss ( E off) can be obtained. It is worth to note that owing to reshaped electric field in the new structure, the excess carriers of the drift region could be removed more quickly. Furthermore, larger G of the VLD layer improves the tradeoff between breakdown voltage and turn-off loss. The results of 2-D simulation indicate that the E off of the proposed device can reduce by 29.4% and 69.7% at 100 A $\cdot$ cm−2 and 200 A $\cdot$ cm−2, respectively, when compared with UPB SOI LIGBT

An Novel Thin Layer SOI Carrier-Stored Trench LIGBT With Enhanced Emitter Injection

An novel thin layer SOI carrier-stored (CS) trench lateral insulated gate bipolar transistor (TLIGBT) with diode-clamped P-shield layer is proposed. The potential of the P-shield layer is clamped by two series-connected diodes. Therefore, the reverse voltage is sustained by the P-shield/N-drift junction rather than the P-base/CS junction during the off-state. Thus, the doping concentration of the carrier-stored layer ( ${N} _{\mathrm{ cs}}$ ) can be significantly improved without compromising the breakdown voltage. Hence, an ultra-low on-state voltage drop ( ${V} _{\mathrm{ on}}$ ) can be obtained. Besides, the two series-connected diodes clamp the drain-to-source voltage of the intrinsic n-MOS in the TLIGBT, which leads to an ultra-low saturation current and improves the short-circuit withstand capability. The simulation results indicate that the turn-off loss ( ${E} _{\mathrm{ off}}$ ) at ${V} _{\mathrm{ on}} = 1.37$ V is reduced by 28.8% and 21% compared with those of the conventional carrier-stored LIGBT A and LIGBT B, respectively. Moreover, the saturation current density is reduced by over 53.3% and the short circuit withstand time is improved by more than 2 times than those of the conventional and state-of-the-arts.

Area-Efficient and Snapback-Free SOI LIGBT With L-Shaped Extraction Path

A novel area-efficient snapback-free silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed and investigated for the first time in this paper. The device features an N+ anode, three separated P+ anodes, and a P-buried layer (PBL) in the N-buffer of the anode region. The N-buffer between all these components above forms a 3-D L-shaped extraction path. The L-shaped extraction path not only makes the device area-efficient but also increases the anode distributed resistance ( ${R} _{\mathrm{ SA}}$ ). Therefore, the snapback effect could be suppressed, and the tradeoff between the on-state voltage ( ${V} _{\mathrm{ on}}$ ) and turn-off energy ( ${E} _{\mathrm{ off}}$ ) is improved effectively. Simulation results show that the proposed device eliminates the snapback effect with 63% and 77% reduction of the anode region area compared with the segmented trenches in the anode region (STA) LIGBT and the separated shorted anode (SSA) LIGBT, respectively. At the same ${V} _{\mathrm{ on}}$ , the LEP LIGBT reduces the turn-off time ( ${t} _{\mathrm{ off}}$ ) and ${E} _{\mathrm{ off}}$ by 40% and 28%, respectively, compared with the STA LIGBT. Moreover, at the same ${E} _{\mathrm{ off}}$ , the LEP LIGBT reduces ${V} _{\mathrm{ on}}$ by 17%, compared with the SSA LIGBT.

A Novel Double-RESURF SOI Lateral TIGBT With Self-Biased nMOS for Improved <inline-formula> <tex-math notation="LaTeX">${V}_{\text{CE(sat)}}$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">${E}_{\text{off}}$ </tex-math> </inline-formula> Tradeoff Relationship

A novel double-reduced surface field (RESURF) silicon-on-insulator (SOI) lateral trench insulated-gate bipolar transistor (LTIGBT) with self-biased nMOS is proposed and investigated by simulation. During the turn-on transient, the self-biased nMOS is turned-off, and the p-top region is floating, and therefore the conductivity modulation in the drift region on the emitter side can be enhanced to achieve a low on-state voltage ( ${V}_{\textsf {CE(sat)}}$ ). During the turn-off transient, the self-biased nMOS is turned on, and the p-top region is connected to the emitter, which effectively reduces its turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). As a result, the proposed LTIGBT realizes superior ${V}_{\textsf {CE(sat)}}$ – $E_{ \mathrm{\scriptscriptstyle OFF}}$ tradeoff relationship than both the conventional SOI trench-gate lateral insulated-gate bipolar transistor (LIGBT) (LTIGBT-A) and the double-RESURF SOI trench-gate LIGBT (LTIGBT-B). Simulation results reveal that, with the identical ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ of 0.25 mJ/cm2, ${V}_{\textsf {CE(sat)}}$ of the proposed LTIGBT is 1.08 V, which is 11.4% and 32.5% lower than those of LTIGBT-A and LTIGBT-B, respectively; with the identical ${V}_{\textsf {CE(sat)}}$ of 1.1 V, ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ of the proposed one is 0.19 mJ/cm $^{\textsf {2}}$ , which is 70% and 89% lower than the other two, respectively. Furthermore, the proposed device exhibits a lower saturation current.

Optimization of <inline-formula> <tex-math notation="LaTeX">${V}_{\text{CE}}$ </tex-math> </inline-formula> Plateau for Deep-Oxide Trench SOI Lateral IGBT During Inductive Load Turn-OFF

Collector–emitter voltage ( ${V}_{\textsf {CE}}$ ) plateau of the 500-V deep-oxide trench (DOT) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) during inductive load turn-off is investigated and optimized for the first time in this paper, aiming to reduce the turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). The mechanism of ${V}_{\textsf {CE}}$ plateau is revealed by TCAD simulation. In conventional DOT SOI-LIGBT, the large number of stored carries in the silicon region beneath the DOT (Region I) hinders the extension of depletion layer and slows down ${V}_{\textsf {CE}}$ rising during turn-off, leading to a plateau phase. A novel DOT SOI-LIGBT with dual-controllable vertical field plates (CPFs) is proposed to shorten the ${V}_{\textsf {CE}}$ plateau. The dual CPFs are arranged in the DOT and their electric potentials ( ${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$ ) are controlled through the connection with scrolled resistive polysilicon filed plate. By adjusting ${V}_{\textsf {F} 1}$ and ${V}_{\textsf {F} 2}$ , the accelerated depletion and extraction of stored carriers in Region I can be realized, resulting in a short ${V}_{\mathbf {CE}}$ plateau duration. The ${V}_{\mathbf {CE}}$ plateau duration can be decreased from 156 ns for the conventional SOI-LIGBT to 60 ns for the proposed SOI-LIGBT with ${V}_{F1} = 0$ V and ${V}_{\textsf {F}2} = {0.5}\,\,{V}_{\textsf {CE}}$ . The proposed DOT SOI-LIGBT achieves an ${E}_{ \mathrm{\scriptscriptstyle OFF}} $ 59.2% lower than the conventional DOT SOI-LIGBT at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 2.96 V.

A Carrier Stored SOI LIGBT With Ultralow ON-State Voltage and High Current Capability

A novel carrier stored (CS) SOI lateral insulated gate bipolar transistor (LIGBT) with ultralow on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and high current capability is proposed and its electronic performance is investigated by simulation. The device features the CS layer and the trigate (TG) structure, named TGCS LIGBT. The CS effect in the on-state delivers an ultralow ${V}_{ \mathrm{\scriptscriptstyle ON}}$ . The TG is employed to increase the channel density and modulate the current distribution, further reducing the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and achieving high current capability. Moreover, TG assists in depleting the highly doped CS layer, which enhances the conductivity modulation and maintains high breakdown voltage. The extended P+ in the comb-shaped P+ region provides a low-resistance hole current path, and thus enhances the latch-up immunity. At the same turn-off loss, the TGCS LIGBT reduces the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 32.5% and 36.4% compared with the tridimensional channel (TC) LIGBT and the conventional (Con). LIGBT, respectively. The TGCS LIGBT exhibits high current capability, which has an improvement of 151% and 26.8% compared with those of the Con. LIGBT and the TC LIGBT, respectively. The TGCS LIGBT shows a little better short-circuit capability than does the Con. LIGBT.

A Snapback-Free Fast-Switching SOI LIGBT With an Embedded Self-Biased n-MOS

A 600-V snapback-free fast-switching silicon-on-insulator lateral insulated gate bipolar transistor with an embedded self-biased n-MOS (SBM) is proposed and investigated by simulations. The proposed device features an n-MOS which consists of the N+ anode, p-layer, N-buffer, and the anode trench gate (ATG) embedded between the P+ anode and N+ anode. It is worth noting that the ATG is driven by the anode, without any additional control circuits. At the initial conduction stage, p-layer/N-buffer junction acting as electron barrier contributes to snapback-free with a reduced cell pitch. Simultaneously it provides an extra built-in path to extract electrons at the turn-OFF stage, which hence reduces the turn-OFF energy loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) and increases the switching speed. Furthermore, the hole leakage current of the SBM LIGBT in the blocking state is suppressed due to the electron accumulation/inversion formed along the sidewall of the ATG, avoiding triggering the P+NP transistor and thus increases the breakdown voltage by 11% in comparison with that of the conventional LIGBT. Simulation results show that the SBM LIGBT reduces ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ by 31% and 43% compared to the conventional LIGBT with the same on-state voltage drop ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ), at the load current of 100 and 200 A/cm2, respectively.

A snapback-free TOL-RC-LIGBT with vertical P-collector and N-buffer design**Project supported by the National Natural Science Foundation of China (Grant No. 61604027), the Basic and Advanced Technology Research Project of Chongqing Municipality, China (Grant No. cstc2016jcyjA1923), the Scientific and Technological Research Foundation of Chongqing Municipal Education Commission, China (Grant No. KJ1500404), the Youth Natural Science Foundation of Chongqing University of Posts

A reverse-conducting lateral insulated-gate bipolar transistor (RC-LIGBT) with a trench oxide layer (TOL), featuring a vertical N-buffer and P-collector is proposed. Firstly, the TOL enhances both of the surface and bulk electric fields of the N-drift region, thus the breakdown voltage (BV) is improved. Secondly, the vertical N-buffer layer increases the voltage drop VPN of the P-collector/N-buffer junction, thus the snapback is suppressed. Thirdly, the P-body and the vertical N-buffer act as the anode and the cathode, respectively, to conduct the reverse current, thus the inner diode is integrated. As shown by the simulation results, the proposed RC-LIGBT exhibits trapezoidal electric field distribution with BV of 342.4 V, which is increased by nearly 340% compared to the conventional RC-LIGBT with triangular electric fields of 100.2 V. Moreover, the snapback is eliminated by the vertical N-buffer layer design, thus the reliability of the device is improved.

Low-Loss 800-V Lateral IGBT in Bulk Si Technology Using a Floating Electrode

An 800V rated lateral insulated-gate bipolar transistor (LIGBT) for high frequency and low-cost applications is proposed. This LIGBT features a new method of adjusting the bipolar gain by using floating N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions connected by a floating electrode in front of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> collector. This floating structure lowers the injection efficiency at the collector side of the device, resulting in a very significant decrease in turn-off time and substantially lower turn-off losses. The device was fabricated in a 0.5μm bulk silicon CMOS technology at a commercial foundry without additional processing steps or process optimisation. Tests on fabricated devices showed equivalent Rdson below 70 mQ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 125 °C with switching times as low as 250 ns at 125 °C. The novel LIGBT device showed avalanche capability and low gate capacitance and was used for the first time, in an AC/DC converter operating at 200 kHz allowing significant improvements in performance, compactness, and reduced component count.

Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device

The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the emitter side due to the crowded current made by the small N+ emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the emitter vertically, which is helpful for reducing surface current density. Considering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal–oxide–semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.

Hot-carrier-induced current capability degradation and optimization for lateral IGBT on thick SOI substrate

In this paper, the hot-carrier-induced current capability degradation of a 600 V lateral insulated gate bipolar transistor (LIGBT) on thick silicon on insulator (SOI) substrate is investigated. Our experiments found that, for the SOI-LIGBT, the worst stress condition is the maximum gate voltage (Vgmax) condition and the current degradation is dominated by the damages in the channel region under the Vgmax stress condition. However, further analyses show that the influence of channel region damages on the collector current degradation increases with the increase of measured collector voltage and is maximum in the current saturation region. Therefore, in our opinion, the hot-carrier-induced current capability degradation of the SOI-LIGBT should be evaluated by the degradation of saturation current under the Vgmax stress condition. In addition, a novel SOI-LIGBT structure with an external p-type region was also proposed, which can alleviate the damage in the channel region by reducing the lateral electric field peak. Our experimental results demonstrate that the proposed structure could optimize the hot-carrier reliability effectively with the other characteristics maintained.

Impact of underfill and other physical dimensions on Silicon Lateral IGBT package reliability using computer model with discrete and continuous design variables

An effort to design and build a prototype LED driver system which is energy efficient, highly compact and with few component count was initiated by a consortium UK universities. The prototype system will be based on Silicon Lateral IGBT (LIGBT) device combined with chip on board technology. Part of this effort, finite element modelling and analysis were undertaken in order to mitigate the underfill dielectric breakdown failure and solder interconnect fatigue failure of the LIGBT package structure. Electro-static analysis was undertaken to predict the extreme electric field distribution in the underfill. Based on electro-static analysis, five commercial underfill were selected for thermo-mechanical finite element analysis on solder joint fatigue failure prediction under cyclic loading. A design optimisation analysis was endeavoured to maximise the solder interconnect reliability by utilising a computer model with continuous variable (physical dimensions) and discrete variables (underfill type) and a stochastic optimiser such as multi-objective mixed discrete particle swarm optimisation. From the optimisation analysis best trade off solution are obtained.

A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode

A snapback-free fast-switching lateral insulated-gate bipolar transistor (LIGBT) with low power loss and high ruggedness is proposed and investigated by simulation. The proposed device features a polysilicon regulative resistance (PR) and a trench cathode (TC), named PRTC LIGBT. The PR is employed to not only suppress the snapback effect by regulating the voltage drop between P+ anode and N-buffer, but also improve the tradeoff between the on-state voltage drop ( $\text{V}_{ \mathrm{\scriptscriptstyle ON}})$ and turn-off loss ( $\text{E}_{ \mathrm{\scriptscriptstyle OFF}})$ . The TC widens the hole current path and decreases the distributed resistance under N+ cathode, and thus delivers a high latch-up ruggedness. Additionally, the PRTC LIGBT exhibits a blocking characteristic irrelevant to P+ anode concentration (NA), like a p-i-n diode (P-well, N-drift, and N-buffer), owing to its undepleted N-buffer region. Simulation results show that the PRTC LIGBT eliminates the snapback and reduces the $\text{E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 28% compared to the segmented trenches in the anode (STA) region LIGBT. Its short-circuit time is prolonged by 53% and 40% compared to those of the STA LIGBT and PR LIGBT (without TC), respectively.

Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC

A novel composite device structure named self-adjust conductivity modulation lateral insulated gate bipolar transistor (SCM-LIGBT), including normal LIGBT region (NLT region), the EM-nMOS region (ENM region), and the series diode region (DIO region), is proposed in this paper. By adding the enhanced-mode nMOS region and the series diodes region, the parasitic NPN transistor (NPN) bipolar structure in the normal LIGBT structure can be triggered in on-state and the conductivity modulation is dramatically enhanced, which leads to the improvement on the current capability and the forward voltage. In addition, due to the base voltage of the parasitic NPN bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe operating area. Numerous simulations and measurements are presented to investigate the electrical characteristics of the proposed structure. The length of the fabrication SCM-LIGBT is $78.5~\mu \text{m}$ , and the width of the DIO and NLT is 830 $\mu \text{m}$ , while the width of the ENM is $4100~\mu \text{m}$ . The results demonstrate that the proposed SCM-LIGBT achieves a high-current capability ( ${J}_{A})$ of 2428 A/cm2 at ${V}_{G}= 10$ V, a low on-state voltage drop of 1.15 V at ${J}_{A}= 150$ A/cm2 with its breakdown voltage of 590 V.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) and near the collector side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) are shallower than that of the trench (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ) located in the silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> , resulting in a lower on-state voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and N-buffer region (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is reduced from 9 μm for the DDOT SOI-LIGBT to 5 μm for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) 36.1% lower than the DDOT SOI-LIGBT at the same V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> of 1.53 V.

Turn-off failure in multi-finger SOI-LIGBT used for single chip inverter ICs

In this paper, the clamped inductive turn-off failure of the Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multiple fingers under high-voltage and high-current conditions is investigated. First, the measured turn-off waveforms combining with the on-state I-V characteristics of the failed device are discussed to distinguish the probable cause of the failure. Then, two-dimensional (2-D) electrothermal simulations are performed to reproduce the failure by using Sentaurus TCAD. The failure is originated from an inhomogeneous depletion behavior among the paralleled fingers during the turn-off, which gives rise to the non-uniform current-sharing and the subsequent current crowding in single finger. As a result, the latch-up of the device takes place. The simulation indicates that the current crowding is formed mainly through an internal path in the silicon. In order to verify the failure mechanism, an improved device with deep-oxide trenches arranged between the adjacent fingers is fabricated. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions.

Low-Loss SOI-LIGBT With Dual Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

ESD robustness concern for SOI-LIGBTs with typical latch-up immunity structures

The ESD robustness of the lateral insulated gate bipolar transistors based on SOI substrate (SOI-LIGBTs) with two typical latch-up immunity structures, including P-sink well and P++ doping layer beneath the emitter, are compared and discussed. The SOI-LIGBT with P-sink well has the strong ESD robustness and fails at the collector side due to the concentrated current density. The SOI-LIGBT with P++ doping layer fails before it is triggered due to the large surface electric field at the PN junction between P-body and N-drift regions. Considering the comprehensive performances of both devices, the SOI-LIGBT with P-sink well is suggested as the output device, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

A U-Shaped Channel SOI-LIGBT With Dual Trenches

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( ${V}_{\mathrm{\scriptscriptstyle ON}}$ ) and turn-OFF loss ( ${E}_{\mathrm{\scriptscriptstyle OFF}})$ . The proposed SOI-LIGBT offers an ${E}_{\mathrm{\scriptscriptstyle OFF}}~52.3$ % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same ${V}_{\mathrm{\scriptscriptstyle ON}}$ of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2.