ESD robustness concern for SOI-LIGBTs with typical latch-up immunity structures

Abstract

The ESD robustness of the lateral insulated gate bipolar transistors based on SOI substrate (SOI-LIGBTs) with two typical latch-up immunity structures, including P-sink well and P++ doping layer beneath the emitter, are compared and discussed. The SOI-LIGBT with P-sink well has the strong ESD robustness and fails at the collector side due to the concentrated current density. The SOI-LIGBT with P++ doping layer fails before it is triggered due to the large surface electric field at the PN junction between P-body and N-drift regions. Considering the comprehensive performances of both devices, the SOI-LIGBT with P-sink well is suggested as the output device, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.