Lateral Silicide Growth Research Articles

SB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant Segregation

MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator

Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p+ source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 μ/spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 41/42 GHz were demonstrated for 0.5×10μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> transistors.

Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies

Ni-silicide phase formation with and without a Ti capping layer was studied by sheet resistance, x-ray diffraction and transmission electron microscopy. Ni monosilicide is found to be the stable phase in a temperature range from 400 to 600 °C. At lower temperatures the Ni2Si phase is found to be present. For temperatures higher than 700 °C NiSi is converted into NiSi2. Pyramidal NiSi2 precipitates were found to grow epitaxially along the Si〈111〉 planes for annealing temperatures as low as 310 °C. The epitaxial NiSi2 grains were found to disappear when the annealing temperature is increased. Stress buildup during Ni silicidation was measured in situ and could be correlated to the formation of the different Ni-silicide phases. The stress induced by Ni-monosilicide formation compares favorably to the stress induced by Co disilicide and Ti disilicide. The average silicon consumption required to obtain a certain sheet resistance was found to be 35% lower for Ni monosilicide compared for Co disilicide. It was found that a two-step process is needed to obtain complete conversion to the preferred Ni-monosilicide phase without lateral silicide growth. The sheet resistance of Ni-silicided narrow poly-Si and active area lines was found to be low, even when Ni silicide was formed without a Ti cap. No degradation of the Ni silicide on the narrow poly-Si lines was observed when the silicidation temperature was increased to 600 °C. The reverse bias leakage of shallow Ni-silicided and Co-silicided square diodes was compared for varying junction depths and varying silicide thicknesses. For similar junction depth and similar sheet resistance, a lower reverse bias leakage current was obtained for a Ni-silicided junction compared to its Co-silicided counterpart. This may be attributed to the reduced Si consumption of Ni monosilicide compared to Co disilicide.

Comparative Study on Lateral Silicide Growth in Self-Aligned Ti and Co Silicidation: Interaction and Reactivity with SiO2 and Si3N4

AbstractThe interaction and reactivity of Ti and Co with SiO2 and Si3N4 have been investigated. In the case of Ti salicide, SiO2 sidewall spacer showed no lateral silicide overgrowth and low leakage current between gate and source/drain up to silicidation temperature of 750 1C. However, Si3N4 sidewall spacer showed dopant dependence of the lateral silicide growth and leakage current. This discrepancy between SiO2 and Si3N4 and dopant dependence is closely related to the reactivity. For Co, lateral silicide overgrowth is greatly reduced. Instead, Co films on SiO2 and Si3N4 layer were agglomerated by annealing. An annealing at 1050°C caused not only agglomeration of Co film but penetration of Co agglomerates through the layers. Interestingly, the CoSi2 spike of B type epitaxial and twinned orientation was formed in the Si substrate by the penetrated Co source.

Dopant Effects on Lateral Silicide Growth in Self‐Aligned Titanium Silicide Process

The effects of sidewall material and implanted dopants have been investigated on the lateral silicide growth in self‐aligned titanium silicide process. The sidewall spacer showed no lateral silicide growth and has a low leakage current between gate and source/drain up to silicidation temperatures of 750°C. This was found to be due to released oxygen from the sidewall spacer into titanium film, which impedes silicon diffusion over the . However, the sidewall spacer showed dopant dependence of the lateral silicide growth and leakage current. This discrepancy between and results from the fact that nitrogen has lower reactivity with titanium and less suppression of the lateral silicide growth than oxygen. The lateral silicide growth and leakage current in decreased in the order of dopant species of and P. Released dopants from can affect the silicon diffusion, and this is closely related to the reactivity of each dopant with titanium.

Nanoscale Observation of a Grain Boundary Related Growth Mode in Thin Film Reactions

We report the atomic scale observation of a thin film growth mode related to grain boundaries in multilayers of polycrystalline gold and amorphous silicon. Using differential scanning calorimetry, in situ x-ray diffraction, and high-resolution electron microscopy, we observe silicide nucleation to take place at grain boundaries in the polycrystalline gold films followed by lateral silicide growth parallel to gold/silicon interfaces. This growth mode is related to solid-state reactions at low temperatures where atomic transport is restricted to grain and interphase boundaries. It demonstrates the importance of thin film microstructure for phase selection during thin film reactions at low temperatures.

Formation of self-aligned CoSi2 on selective epitaxial growth silicon layer on (001)Si inside 0.1–0.6 μm oxide openings prepared by electron beam lithography

The self-aligned formation of CoSi2 was achieved on the selective epitaxial growth (SEG) silicon layer on (001)Si inside 0.1–0.6 μm oxide openings prepared by electron beam lithography. The uniform, high quality SEG Si layer was grown by ultrahigh vacuum chemical vapor deposition at 560 °C with Si2H6. Self-aligned CoSi2 film without lateral growth of silicide was grown on the SEG Si layer by rapid thermal annealing at 700 °C in N2 ambient. The successful integration of the self-aligned CoSi2 and SEG of Si processes promises to be a viable process technology for the future deep submicron devices.

Formula omitted] bilayers in salicide technology: electrical evaluation

A detailed investigation of the applicability of Ti Co bilayers for the salicide technology is presented. In the first place the silicide formation on poly-Si gate lines using Ti Co bilayers has been studied. It is demonstrated that lateral silicide growth over the spacers can be avoided by making use of a two-step silicidation. In addition, the thermal stability of CoSi 2 obtained on small poly-Si lines by two-step silicidation of a Ti Co bilayer has been investigated and compared to the thermal stability of CoSi 2 obtained by standard silicidation of a 20 nm Co film. The performance of Ti Co silicidation with respect to bridging has been studied making use of a special yield monitor chip with dedicated bridging cells. Similar as for standard Co silicidation, close to 100% yield numbers are obtained for two-step Ti Co silicidation. Finally, the contact resistance between the silicide and the p + and n + diffusion areas has been evaluated making use of four terminal cross-bridge Kelvin resistor structures. Contact resistivity values were calculated to be in the range of 5−6 × 10 −7 Ω · cm 2 for CoSi 2 p + contacts and in the range of 1–2 × 10 −7 Ω · cm 2 for CoSi 2 n + contacts.

Lateral titanium silicide growth and its suppression using the [formula omitted] bilayer structure

The effects of internal oxygen impurities released from the TiSiO 2 reaction on the lateral silicide growth using the a-Si Ti bilayer structure are presented. The lateral silicide growth can be effectively retarded by internal oxygen impurities using a-Si Ti bilayer process after silicidation at a temperature below 700°C. Compared with the simultaneously processed single Ti layer process, it is observed that both high-level oxygen impurities and their redistribution in the possible Si diffusion paths play the same important role on the suppression of the lateral silicide growth. Finally, the oxygen-redistribution-dependent kinetics is developed to give a self-consistent explanation for the experimental observations from both the single Ti layer process and the a-Si Ti bilayer process.

Spatially confined nickel disilicide formation at 400 °C on ion implantation preamorphized silicon

The localized formation of continuous silicide layers via solid state reaction of nickel atoms with ion implantation preamorphized silicon is described. Ni films 12 nm thick were evaporated on 65 nm deep amorphized surface layers. The silicidation reaction was induced by two stage thermal annealing at 360 and 400 °C, well below the solid phase epitaxial regrowth temperature for amorphous Si and the normal NiSi2 formation temperature. Rutherford backscattering with channeling, XTEM, and four-point-probe measurements were used to determine the structure, interfacial morphology, composition, and resistivity of the silicide films. After the lower temperature annealing stage a continuous layer of NiSi2 is formed with an underlying residual amorphous region located above the crystalline substrate. During a second annealing the residual amorphous areas recrystallize epitaxially with respect to the substrate via lateral silicide growth. The process leads to formation of a continuous 35 nm thick nickel disilicide layer completely confined within the original amorphous region. Silicide resistivity was 44 μΩ cm. The process may be viewed as a low-temperature process enhancement to self-aligned silicide (SALICIDE) technology since silicide growth proceeds only on preamorphized areas of the silicon substrate.

Formation of self-aligned cobalt silicide in normal flow nitrogen furnace

Cobalt can be completely transformed into cobalt silicide during annealing in a normal flow nitrogen furnace above a certain temperature which depends on the thickness of the cobalt film deposited on the silicon substrate. For a 400 Å cobalt film this temperature is 500 °C and for a 1500 Å cobalt film it is 650 °C. Loading the wafer into the furnace tube is a critical step to prevent the cobalt from oxidation before silicidation in the annealing process. Lateral growth of silicide is not observed using this silicidation scheme. The cobalt oxide together with the underlying cobalt over the silicon oxide can be removed by hot 3HCl + H 2O 2 + 3H 2O solution if the annealing is performed at a temperature below 650 and 900 °C for a cobalt film thickness of 400 and 1500 Å respectively. The optimum condition for practical silicide formation is defined. The products and microstructure over the silicon and silicon oxide are characterized by X-ray diffraction spectra, Auger electron spectroscopy depth profiles, sheet resistance measurements and scanning electron microscopy inspection.

Cobalt disilicide formed by rapid thermal annealing and throughmetal arsenic implantation

Cobalt disilicide CoSi2 of a specific resistivity of 23 μω was formed by the solid phase reaction of cobalt and silicon in the phase sequence of Co2Si, CoSi, and CoSi2 by use of rapid thermal annealing. The through-metal arsenic implantation caused the mixing of cobalt with the silicon substrate and the formation of cobalt silicides. A significant lateral growth of cobalt silicides was observed in samples subjected to one-step rapid thermal annealing process at 900 °C without through-metal ion implantation. Ion beam mixing reduced this lateral silicide growth efficiently, but resulted in a higher density of cobalt atoms remaining in the silicon oxide film than after rapid thermal annealing, as revealed by vapor phase decomposition atomic absorption spectroscopy.

Formation of cobalt silicide by ion beam mixing

The formation of cobalt silicides by arsenic ion implantation through a cobalt film which causes a mixing of the metal with the silicon substrate was investigated. Furthermore, cobalt suicides were formed by rapid thermal annealing (RTA). Sheet resistance and silicide phases of implanted Co/Si samples depend on the As dose. Ion beam mixing at doses higher than 5 × 10 15 cm −2 and RTA at temperatures T ⩾ 900° C result in almost equal values of R s. RBS and XRD spectra of these samples illustrate the formation of a homogeneous CoSi 2 layer. Significant lateral growth of cobalt silicide beyond the edge of patterned SiO 2 was observed in samples which were only subjected to an RTA process ( T ⩾ 900 ° C), while this lateral suicide growth could be reduced efficiently by As implantation prior to RTA.

Cobalt silicide formation caused by arsenic ion beam mixing and rapid thermal annealing

Ion beam mixing and rapid thermal annealing (RTA) were used to prepare low resistivity (≈ 23 μΩ cm) cobalt disilicide, CoSi 2, layers. Through-metal As + ion implantation causes some mixing between Co and Si resulting in the formation of cobalt suicides. By using RTA, the silicide formation happens in the phase sequence Co 2Si, CoSi and CoSi 2. Samples which were only subjected to a one-step high temperature RTA process ( T ≥. 900°C, 1s) show significant lateral growth of cobalt suicides. By ion beam mixing of Co and Si this lateral silicide growth could be reduced efficiently. Furthermore one can get a very homogeneous CoSi 2 layer.

Window size effect on lateral growth of nickel silicide

Window size effect on lateral growth of nickel silicide in contact windows cut into oxide grown on Si (100) is studied. The growth rate is found to be independent of window size and follows the diffusion-limited process with activation energy of 1.5 eV. The Si erosions are observed to grow due to predominant Si diffusion for vacuum anneal above 600 °C. This phenomenon becomes greatly pronounced with fine windows of 2 μm in diameter. We attribute this to (i) an enhanced stress level in fine windows causing reduction in the growth temperature of epitaxial NiSi2 in the windows and (ii) difference in surface energies of epitaxial NiSi2 formed and the Si substrate resulting in the shrinkage of the epitaxial NiSi2 dimension in the window. No such behavior is observed under identical conditions when Si (111) is used. We believe this is due to the fact that the lateral growth of nickel silicide in this case is about a quarter of that for Ni-Si (100) lateral samples. Finally the technological importance of this study is pointed out.

The Effect of Processing Environment on the Lateral Growth of Titanium Silicide

The purity of the process atmosphere used in the annealing cycles of titanium silicide formation is a very important consideration in the self‐aligned silicide process. The two important problems of oxidation of titanium and lateral growth of titanium silicide are addressed by using nitriding atmospheres containing low levels of oxygen and water. In this work, the lateral growth of titanium silicide in ammonia + nitrogen, nitrogen and argon process atmospheres was investigated. It was observed that ppm levels of oxygen or water in the process environment can cause an unacceptable amount of oxidation of the titanium film. Some comments on the mechanism of lateral growth containment are also included.

Suppression of lateral Ti silicide growth by ion beam mixing and rapid thermal annealing

One of the most important issues in the self-aligned silicide technology has been lateral silicide formation over the sidewall oxide spacers. In this work, the lateral silicide growth has been considerably suppressed by the use of ion beam mixing and rapid thermal annealing. Metal-oxide-semiconductor transistors fabricated using this technology show good electrical characteristics with negligible conduction between gate and source/drain electrodes.

Self‐Aligned Titanium Silicided Junctions Formed by Rapid Thermal Annealing in Vacuum

New self‐aligned silicided junctions have been developed by rapid thermal annealing in vacuum for applications to VLSI technology. These silicided junctions were investigated in regard to sheet resistance, junction depth, junction leakage current, and impurity depth profiles. After Ti film (35 nm) was deposited by dc magnetron sputtering, Si+ was implanted for interface mixing and rapid thermal annealing (RTA) in vacuum (∼10−1 Pa) were performed in temperature range of 550°–750°C. In these temperature ranges, the lateral growth of titanium silicide was prevented. After Si+ implantation through the titanium silicide layer to amorphize the Si substrate, As+ and B+ ions were implanted for n+/p junction, and p+/n junction, respectively. Finally furnace annealing (900°C, 30 min) was performed with a cap CVD oxide. We have successfully fabricated the silicided junctions with the junction depth of 0.12 μm, and the leakage current of (at reverse bias of 5.0V) for n+/p junction and of 0.14 μm, and of for p+/n junction.

Self-aligned titanium silicide device technology by NH3 plasma assisted thermal annealing

The self-aligned titanium silicide device technology has been studied by using NH3 plasma assisted thermal annealing and ion implant through titanium metal or silicide film. Enhanced surface nitridation of titanium by activated species suppresses lateral silicide growth and oxide contamination. NH3 plasma assisted annealing can be used as an effective method to form TiSi2 and activate implanted dopant. P+N junction and P channel metal–oxide–semiconductor field-effect transistor can be produced by boron implant through Ti metal or its silicide and the NH3 plasma assisted thermal annealing.