Lateral Double-diffused MOSFET Research Articles

Extraction Enhanced Lateral Insulated Gate Bipolar Transistor: A Super High Speed Lateral Insulated Gate Bipolar Transistor Superior to Lateral Dobule Difused Metal Oxide Semiconductor Field-Effect Transistor

We have successfully developed novel extraction enhanced lateral insulated gate bipolar transistors (E2LIGBTs) in conventional silicon on insulator (SOI) wafers, which exhibit super-high speed switching of 34 ns turn-off time and a low on-state voltage of 3.7 V at 84 A/cm2 simultaneously with a high breakdown voltage of 738 V. This is the first report showing its superior switching speed and on-resistance compared to conventional lateral double diffused metal oxide semiconductor field-effect transistor (LDMOS). The superior performance is achieved by a new anode structure designed with the proposed E2 concept, which simultaneously achieves enhanced electron extraction and suppression of hole injection at the anode region without life time control. The E2 concept is realized using the anode structure, consisting of a narrow p+-injector and a wide Schottky contact on a lightly doped p-layer over an n-buffer. The switching speed can be controlled by the area ratio of the Schottky area over the injector area.

The Best Control of Parasitic BJT Effect in SOI-LDMOS With SiGe Window Under Channel

The floating-body effect and impact ionization generate excess holes that are amplified by the parasitic bipolar junction transistor (BJT) in silicon-on-insulator lateral double-diffused MOSFETs (SOI-LDMOS) that degrade the transistor performance. In this paper, a novel silicon germanium (SiGe) window LDMOS on SOI (SW-SOI) is reported where the buried oxide under the channel region becomes thinner and a SiGe window has been replaced in order to reduce the hole concentration in the channel and control the BJT effect significantly. The novel features of an SW-SOI are simulated and compared with a conventional LDMOS on SOI (C-SOI). In addition, reduced self-heating effects and higher breakdown voltage have been achieved as compared with the C-SOI. Hence, this paper illustrates the benefits of the high performance SW-SOI device over a conventional one and expands the application of SOI MOSFETs to high temperature.

Effect of silicon window polarity on partial-SOI LDMOSFETs

The effect of silicon window polarity on partial-silicon-on-insulator (PSOI) lateral double-diffused MOSFETs (LDMOSFETs) under high-voltage operation is studied. Different polarities of the silicon window in PSOI LDMOSFETs are analysed to investigate their effects on electrical characteristics: breakdown voltage (BV) and on-resistance (Ron). In PSOI LDMOSFETs, the P-type silicon window is considered as a part of the substrate, whereas the N-type silicon window falls into the drift region, which affects the high-voltage operation of devices. The two-dimensional simulation results show that the BV of PSOI LDMOSFET with P-type window is higher than that of PSOI LDMOSFET with N-type window, whereas the Ron of PSOI LDMOSFET with P-type window is lower than that of PSOI LDMOSFET with N-type window.

A Development Summarization of the Power Semiconductor Devices II

For Silicon-on-Insulator (SOI) Lateral Double-diffused MOSFET (LDMOS), the new technologies, which apply the electric field modulation and charge shielding effects to design new kinds of SOI LDMOS, have been developed in this paper on the basis of several typical lateral high-voltage devices designed by the authors. The trade-off characteristic between the breakdown voltage and the on-resistance is improved further due to the optimized lateral and vertical electric field. Meanwhile, the merits and shortcomings of this new technology are pointed out compared with the conventional methods. This review is the second part for the development summarization of the power semiconductor devices.

High voltage buried step-doping p+ layer silicon-on-insulator lateral double diffused mosfet (SOI LDMOSI) with a back-gate

A high voltage buried step-doping p+layer (BSP+L) lateral double diffused mosfet (LDMOS) on silicon-on-insulator (SOI) with a back-gate is proposed. The new structure is characterized by a BSP+L on the buried oxide under the source. When a high positive bias is applied to the back-gate in the off-state, the depleted BSP+L greatly enhances the electric field in the buried oxide layer under the source. Compared with conventional SOI LDMOS, much higher vertical breakdown voltage is sustained by the buried oxide layer under the source. Moreover, the reduced surface electric field (RESURF) effect is enhanced by the BSP+L, resulting in improvement of lateral breakdown voltage. Simulation results show that breakdown voltage of the new structure is improved greatly while on-resistance is relatively low. Key words: Silicon-on-insulator, breakdown voltage, back-gate, buried step-doping p+ layer.

Dual material insulator SOI-LDMOSFET: A novel device for self-heating effect improvement

The silicon-on-insulator (SOI) power devices show good electrical performance but they suffer from inherent self-heating effect (SHE), which limits their operation at high current levels. The SHE effect is because of low thermal conductivity of the buried oxide layer. In this paper we propose a novel silicon on insulator lateral double diffused MOSFET (SOI-LDMOSFET) where the buried insulator layer under the active region consists of two materials in order to decrease the SHE. The proposed structure is called dual material buried insulator SOI-LDMOSFET (DM-SOI). Using two-dimensional and two-carrier device simulation, we demonstrate that the heat dissipation and the SHE can be improved in a conventional SOI-LDMOSFET by replacement of the buried oxide with dual material buried insulator (silicon nitride and silicon oxide) beneath the active region. The heat generated in the active silicon layer can be flowed through the buried silicon nitride layer to the silicon substrate easily due to high thermal conductivity of silicon nitride. Furthermore, the channel temperature is reduced, negative drain current slope is mitigated and electron and hole mobility is increased during high-temperature operation. The simulated results show that silicon nitride is a suitable alternative to silicon dioxide as a buried insulator in SOI structures, and has better performance in high temperature.

Analysis and Fabrication of an LDMOS With High-Permittivity Dielectric

A lateral double-diffusion MOSFET with a uniform high-permittivity (HK) dielectric field plate (FP) is manufactured and presented in this letter. The HK dielectric FP is capable of cutting both electric peak fields at the channel p-n junction and the edge of FP, providing higher breakdown voltage (BV) based on a novel mechanism. The Pb(Zr0.53, Ti0.47)O3 (PZT) is taken as the HK dielectric material for its large preanneal permittivity. The test results indicate that, based on two identical devices except for the dielectric material, the BV of the one with PZT FP is more than three times of that of the counterpart with a SiO2 dielectric, approximately 350 and 100 V, respectively.

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V DS = 30 V and gate–source voltage V GS = 10 V.

Impact of Drift Gap, <I>N</I>-Layer, and Deep N<SUP>+</SUP> Sinker on Breakdown Voltage and Saturation Current of Lateral Double-Diffused Metal Oxide Semiconductor Transistor

In this paper, we discuss on the optimal design of a High-Side n-channel Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor (LDMOSFET) whose breakdown voltage is over 100 V with 0.35 microm Bipolar-CMOS-DMOS (BCD) process. The proposed nLDMOSFET has been fabricated and tested in order to confirm the features of a deep N+ sinker and a gap of between the drift region (DEEP N-WELL) and the center of the source. The surface is implanted by the N-layer for high breakdown voltage and simultaneously the low specific on-resistance. The computer simulation of the proposed High-Side LDMOS exhibits BVdss of 115 V and Ron,sp of as low as 2.20 m ohms cm2, which is consistent with the experimental results.

A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that the BV of double step partial silicon on insulator is nearly 69% higher and alleviates SHEs 17% in comparison with its single step partial SOI counterpart and nearly 265% higher and alleviate SHEs 18% in comparison with its conventional SOI counterpart.

High-Side nLDMOS Design for Ensuring Breakdown Voltages Over 100 V

We propose a novel n-channel LDMOSFET (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with a breakdown voltage over 100 V under the thermal budget for the conventional 0.35 microm BCD process. We varied the gap between the DEEP N-WELL and the center of the source for optimization and optimized the doping concentration under the surface by the N(ADJUST)-layer in an effort to obtain high breakdown voltage and simultaneously the low specific on-resistance. The fabricated samples of the proposed High-Side n-channel LDMOS structure exhibit BVdss of 120 V and the specific on-resistance of 2.40 m ohms cm2. We also observed the shift of maximum impact ionization rate from the gate region to the drain side which is considered to strengthen the breakdown characteristics. The numerical simulation revealed that the maximum impact ionization rate of the proposed structure can be reduced down to 18.61 cm(-3) s(-1), while that of the conventional structure being as high as 25.44 cm(-3) s(-1).

A Review of Super Junction LDMOS

Super Junction Lateral Double-diffused MOSFET (SJ-LDMOS) is one of the important attractive devices in high-voltage integrated circuit and power integrated circuit. However, the SJ-LDMOS is generally implemented on a low-resistance substrate, which always suffers from substrate-assisted depletion (SAD) effect, which thus degrades the performance of devices. A number of literatures have been published to solve the SAD effect and improve performance. This review summarizes the developments made in SJ-LDMOS based on bulk silicon, silicon on insulator, and silicon on sapphire in the last 10 years. Finally, the future work what researchers can do on the SJ-LDMOS also has been proposed.

High-side N-channel LDMOS for a High Breakdown Voltage

We propose a novel n-channel LDMOSFET (lateral double-diffused metal oxide semiconductor field effect transistor) structure with a breakdown voltage over 100 V, which was fabricated under the thermal budget of the conventional 0.35-μm industry process. We optimized the engineering parameters, such as the distance of the gap between the DEEP N-WELL and the source region, as well as the doping concentration of the NADJUST-layer, for achieving both the high breakdown voltage and the low specific on-resistance. The fabricated device exhibits a breakdown voltage (BVdss) over 110 V and a specific on-resistance as low as 2.20 mΩ·cm. The robust breakdown characteristics are due to the migration of the location wherein maximum impact ionization occurs from the gate region to the drain side. The numerical simulation revealed that the maximum impact ionization rate of the proposed structure was 2.44 × 10 cm−3s−1 while that of the conventional structure was 6.69 × 10 cm−3s−1.

High Permittivity Dielectric LDMOS for Improved Performance

This paper presents a lateral double diffusion MOSFET (LDMOS) using high permittivity (high-K) material as the dielectric instead of conventional SiO2. The high-K dielectric is capable of cutting the surface peak field of the device, which allows higher drift region doping concentration and results in the improvements of breakdown voltage, on-resistance, and threshold voltage for the device. The mechanism is analyzed in detail and the device behavior with varying parameters are simulated by Medici, whose results demonstrate that device performance is effective improved with the replacement of SiO2 by high-K material.

Double window partial SOI-LDMOSFET: A novel device for breakdown voltage improvement

In this paper we propose novel partial silicon on insulator lateral double diffused MOSFET in order to increase breakdown voltage. The key idea in this work is to decrease common peaks near the drain and gate junctions by producing additional peaks. The proposed structure is called double window partial SOI-LDMOSFET (DWP-SOI). The simulation results show that the breakdown voltage of DWP-SOI can be enhanced about two times as compared to conventional SOI-LDMOSFET(C-SOI) and about 70% as compared to conventional SOI-LDMOSFET with a field plate (CF-SOI). The self-heating effect is also improved in the proposed structure because we have used two windows in buried oxide, which provide a heat conduction path from the active region to the substrate.

Enhancement of Device Performance in LDMOSFET by Using Dual-Work-Function-Gate Technique

In this letter, we propose a new lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) with dual-work-function-gate (DWG) structure fabricated by utilizing silicidation of poly-Si layer. The step-etched poly-Si layer in the source side of the gate was totally converted to Ni-rich silicide, which resulted in a higher work function. On the other hand, in the drain side, only the upper part of the nonetched poly-Si layer was silicided, and the remaining lower part of the poly-Si layer was considered to be a gate with a lower work function. The fabricated DWG-LDMOSFET demonstrated remarkable improvement in device performances, such as 16.7, 16.4, 3.3, and 6.4% improvement in saturation drain current, in field-effect mobility, in subthreshold slope, and in the on resistance, respectively, while keeping almost the same breakdown voltage of 26 V and exhibiting less self-heating effect compared with the conventional single-work-function-gate LDMOSFET.

Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology

In this letter, we report on the reduction of device resistance by up to 36% in lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistors by incorporating trench gates into conventional planar technology. The process and device simulations of this novel device topology are based on a state-of-the-art LDMOS field-effect transistor with a reduced-surface-field extension (buried p-well) for high-voltage applications used for standard IC and ASIC manufacturing processes. Because the well implants can remain unchanged, only a few additional process steps are required for manufacturing such a device. By a straightforward combination of trench- with planar-gate topology, the device resistance can be reduced from 145 to 94 m¿·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the underlying 50-V LDMOS device while fully maintaining its specified blocking properties. The depth of the trench gates just slightly influences the electrical device properties, demonstrating the robustness of trench-gate integration into an existing planar-gate technology.

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 mum exhibits a BV of 500 V and specific on-resistance (R on, sp) of 96 mOmega ldr cm2, yielding to a power figure of merit (BV 2/ R on, sp) of 2.6 MW/cm2 . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.

Behavior of hot carrier generation in power SOI LDNMOS with shallow trench isolation (STI)

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density ( J E) and impact ionization generation rate ( R II) distributions in the devices. The high R II site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.

A High Performance 80V Smart LDMOS Power Device Based on Thin SOI Technology

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.