Latch-up Phenomenon Research Articles

Observation of radiation induced latchup in the readout electronics of NA50 multiplicity detector

During the data taking of the NA50 experiment, the CMOS digital pipeline chips (CDP) used for the readout of the multiplicity detector were exposed to high levels of radiation resulting in an ionizing radiation dose of more than 200 krad and displacement damage equivalent to 1 MeV neutron fluence of more than 5×10 11 eq. neutrons cm −2. Some of these chips showed anomalies of behaviour which we attribute to radiation induced latchup phenomena. Here we present the analysis of the data taken during the 1996, 1998 and 1999 ion runs together with the results of measurements performed in the laboratory.

A new lateral trench-gate conductivity modulated power transistor

In this paper, a new conductivity modulated power transistor called the Lateral Trench-Gate Bipolar Transistor (LTGBT) is presented. This structure incorporates a trench-gate in which the locations of the channel and source in conventional LIGBT have been interchanged. This channel and source arrangement results in significant improvement in latch-up current density. Experimental results indicate that the static and dynamic latch-up current densities are improved by 2.3 and 4.2 times, respectively, compared to those of the LIGBT at a n/sup +/ cathode length of 5 /spl mu/m. Dependence of the latch-up current density of the LTGBT on the design of the n/sup +/ and p/sup +/ cathode regions is examined both numerically and experimentally. The maximum controllable current density is found to be increased when the space between the trench-gate and the p/sup +/ cathode is reduced. Specifically, as the space is decreased to 2 /spl mu/m, no latch-up phenomenon was observed. This nonlatch-up characteristic is obtained at the expense of a slight increase (0.8 V) in threshold voltage.

Analysis and prevention of DRAM latch-up during power-on

The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period.

SEU-hardened storage cell validation using a pulsed laser

Laser tests performed on a prototype chip to validate new SEU-hardened storage cell designs revealed unexpected latch-up and single-event upset phenomena. The investigations that identified their location show the existence of a topology-dependent dual node upset mechanism. Design solutions are suggested to avoid its occurrence.

Single particle-induced latchup

This paper presents an up-to-date overview of the single-event latchup (SEL) hard failure mode encountered in electronic device applications involving heavy ion environment. This phenomenon is specific to CMOS technology. Single-event latchup is discussed after a short description of the effects induced by the interaction of a heavy ion with silicon. Understanding these effects is necessary to understand the different failures. This paper includes a description of the latchup phenomenon and the different triggering modes, reviews of models and hardening solutions, and finally presents new developments in simulation approaches.

Analysis of Latchup susceptibility to internal logical states by using a Laser beam

Experimental results using a laser beam in order to demonstrate the dependence of the latchup sensitivity versus internal logical states are presented. The latch-up triggering mechanisms involved by this method are then numerically analysed by the means of a 2D device simulator in a mixed mode environment. We show that the susceptibility to the latchup phenomenon is increased when the MOS transistor concerned by the parasitic structure is in its low impedance state. It also demonstrates that the usual precautions taken in order to prevent the latchup phenomenon may be efficiently put to the test by using a laser beam contactless testing technique.

The Behavior of Bilateral Latch-Up Triggering in VLSI Electro Static Discharge Damage Protection Circuits

A new latch-up phenomenon that shows symmetrical diac I-V characteristics has been discovered recently. Electrical measurements show that a diac parasitic semiconductor-controlled-rectifier (SCR) device can exist between two adjacent electro static discharge damage (ESD) protection circuits or output buffers. The SCR consists of two parasitic P-N-P-N paths and can easily induce a localized SCR latch-up between two adjacent input or output terminals. This is not similar to traditional latch-up that creates a parasitic P-N-P-N path between power supply and ground pins, but is a new bilateral latch-up path between two adjacent input and output pins. A new latch-up failure mode due to this diac structure, which creates a bilateral path during temperature humidity bias (THB) testing, is discussed. Some suggestions regarding the improvement of this diac latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified diac latch-up lumped element model successfully explains this phenomenon.

New transient characterization of latchup phenomenon in CMOS cell

This paper presents an analysis of the latchup development in CMOS integrated circuits. It sets out the time resolution of the triggering relevant to the different elements involved in the mechanism. So, the importance of the external excitation pulse duration for the triggering process is pointed out and quantified. Based on a lumped element model, the latchup switching current measured at the terminal is completely characterized as a function of the pulse characteristics. An original analytic transient latchup criterion is proposed. Experiments carried out on test structures fabricated in 2 μm, epitaxial, industrial technology as well as SEM observations confirm the validity of the criterion.

Failure analysis of multilevel metallized lsi using optical beam induced current

In order to analyse failures caused in multilevel metallized LSI devices. we developed the OBIC (optical beam induced current) observation technique using an infrared laser incident upon a backside of the chip which appears from a plastic package by being lapped and polished. We analysed the electrical rejects in the reliability stressing of surface mount plastic packages with this technique. The latch-up phenomenon in 4Mbit dynamic RAM with retrograded-well fabricated by a high energy (MeV) ion-implantation was also examined. The high latch-up immunity of the device with retrograded-well is confirmed by this analysis.

Latch-up on CMOS/EPI devices

A dedicated latch-up test system has been developed and was used on two beam lines, the GANIL cyclotron and the IPN Tandem Van de Graaff located in Caen and Orsay (France). The main characteristics of these facilities are presented. Several VLSI circuits were irradiated, and the latchup phenomenon was detected on eight CMOS/EPI devices, revealing various ranges of sensitivity. Recording of the value and rising edge of latchup current was also performed. The problem of whether or not latchup-sensitive circuits should be used for space projects and the need for studies of component design hardening, system design hardening, and latchup rate prediction are addressed. Data are presented on several CMOS/EPI devices demonstrating that an epitaxial layer cannot efficiently achieve latchup immunity for some of the latest technologies. >

Two-dimensional analysis of latch-up phenomena in latch-up-free self-aligned IGBT structures

The latch-up phenomena of insulated-gate bipolar transistors (IGBT) are numerically simulated using a two-dimensional device simulation program for various lengths of the n +-source region and carrier lifetimes, in order to investigate quantitatively the latch-up immunity of a latch-up-free self-aligned IGBT which has essentially the same structure as the power MOSFET proposed recently by Koh and Kim. The key concept behind the numerical simulation is that the parasitic thyristor in the two-dimensional IGBT is equivalent to a p- i- n diode of the same geometry in a conduction state due to conductivity modulation. The simulation shows that the holding current increases by a factor of about 100 when the length of the n +-source region is decreased from about 10 to 1 μm, while the holding current is increased only by a factor of 5 when the lifetime is decreased from 100 to 5 ns. These results clearly demonstrate that the latch-up suppression by reducing the length of the n +-source region as suggested in the proposed latch-up-free IGBT is far more effective than reducing the carrier lifetime.

Cmos latchup theory

AbstractThe purpose of this paper is to study the CMOS latchup phenomenon from a non‐linear circuit theoretic standpoint by using some recently developed results on negative‐resistance devices. We introduce a simple mechanism to describe the latchup phenomenon based on a special circuit topology called feedback structure, which is shown to be responsible for the occurrence of latchup. Several guidelines are proposed to prevent latchup by destroying the feedback structure. In addition to the characterization of the steady‐state behaviour, we use a first‐order circuit model to analyze the latchup dynamics during the turn‐on process and give a stability analysis of the circuit dynamics. All existing techniques to prevent latchup are shown to follow naturally from our guidelines, which are derived using nonlinear circuit theory.

Parasitic lateral bipolar transistors in CMOS

The electrical behaviour of lateral bipolar transistors has a large effect on latch-up phenomena; in particular in the region between low level and high level injection, where the parasitic thyristor is switching on. By solving the continuity equation in this region under some approximations the base and collector current can be calculated rather accurately if the lifetime of the minority carriers in the base is known. The influence of this parameter is very important; therefore a few measurement techniques are discussed and the influence of the lifetime on the electrical characteristics is shown. Finally a comparison between the holding current, implementing and neglecting the odd shape of the beta in the transition region between high and low level injection, is made.

Dynamics of heavy-ion-induced latchup in CMOS structures

Heavy-ion-particle-induced latchup phenomenon in CMOS parasitic p-n-p-n structures is analyzed using a two-dimensional transient device simulator. In the study, the dynamics of the latchup turn-on behavior in a conventional bulk structure are investigated in detail. Moreover, the relation between the terminal currents and the behavior of inner variables such as carriers and potential is also described. Relative latchup immunity for several device structures is also studied. From the points of the decoupling of the parasitic n-p-n and p-n-p transistors, which is the key factor for preventing latchup, the p/sup -/-p/sup +/ epitaxial wafer with and without guard bands is discussed in comparison with the conventional structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Techniques for latch-up analysis in CMOS IC's based on scanning electron microscopy

Scanning electron microscopy techniques for the characterization of latch-up phenomena in CMOS integrated circuits are reported, critically rewieved and compared with experimental techniques described in the literature, based on infra-red and scanning laser microscopy. Several examples of application are presented to demonstrate the capability of a SEM system for practical layout debugging. Described SEM techniques comprise: (a) sensitivity analysis by means of ebeam induced current, with digital control of the beam position and beam blanking to avoid MOS damaging; (b) identification of latch-up sites in steady-state by Digital Differential Voltage Contrast; (c) study of transient and triggering phenomena and localization of latch-up firing points by means of stroboscopic voltage contrast.

Observation of latch-up time evolution in CMOS IC's by means of SEM stroboscopic voltage contrast techniques

SEM stroboscopic voltage contrast techniques allow one to observe with high voltage resolution the temporal and spatial evolution of latch-up phenomena from the firing event to the final condition. In particular, the authors show by means of an example that in a CMOS IC the firing point may be different from the latch-up site in steady state. Only dynamic observations, therefore, allow a complete understanding of latch-up phenomena and an effective correction of IC layout.

A new MOS-gate bipolar transistor for power switches

A new monolithic integrated power device, the MOS-gate transistor (MGT), which consists of a bipolar transistor for an output stage and two MOSFET's for a driver stage, has been investigated. The purpose of the study was to obtain a power switch having characteristics of an easy drive, a short turn-off time, and a high current density. The developed device structure featured the integration of three elements into a small cell from a large number of which the MGT chip was constructed. This device had no parasitic thyristor, making it free from the latchup phenomenon. Unit MGT devices with a blocking voltage of 400-500 V were fabricated. A high current density of 90 A/cm2at a collector-emitter voltage of 2 V and a short turn-off time of less than 1 µs were obtained. The MGT devices, which contained 36 cells, were fabricated with chip sizes of 5 × 5 mm. They exhibited a blocking voltage of 500 V, on-state voltage of 2.3 V at a current of 10 A, and turn-off time of 0.5 µs at 150°C.

A new self-aligned well-isolation technique for CMOS devices

This paper presents the development of a new well-isolation technique for advanced CMOS LSI's. The technique comprises narrow deep trench fabrication utilizing undercut, in addition to silicon-oxide cap formation, which leaves a cavity. The predominant feature of this technique is that well isolation self-aligned to the well region is realized utilizing the trench fabrication technique. Additionally, no crystal defects are observed around the well isolation even after 1000°C annealing following silicon-oxide cap formation. Since the well isolation produced also prevents the latchup phenomenon from occurring due to its depth, this technique enables the CMOS device dimensions to be considerably reduced.

Observation of latch-up phenomena in CMOS ICs by means of digital differential voltage contrast

The latch-up phenomenon in CMOS ICs is studied by means of a SEM observation technique that is based on capacitively coupled voltage contrast and is characterized by digital beam control and image acquisition. Passivated devices are studied at low beam energies, without interfering with their electrical behavior. The comparison between images taken in the latched and nonlatched state allows reliable identification of the latch-up current paths and thus of the latched site. The performance of the technique is demonstrated by three examples which refer to one standard and two custom CMOS ICs.

Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.