Two-dimensional analysis of latch-up phenomena in latch-up-free self-aligned IGBT structures

Abstract

The latch-up phenomena of insulated-gate bipolar transistors (IGBT) are numerically simulated using a two-dimensional device simulation program for various lengths of the n +-source region and carrier lifetimes, in order to investigate quantitatively the latch-up immunity of a latch-up-free self-aligned IGBT which has essentially the same structure as the power MOSFET proposed recently by Koh and Kim. The key concept behind the numerical simulation is that the parasitic thyristor in the two-dimensional IGBT is equivalent to a p- i- n diode of the same geometry in a conduction state due to conductivity modulation. The simulation shows that the holding current increases by a factor of about 100 when the length of the n +-source region is decreased from about 10 to 1 μm, while the holding current is increased only by a factor of 5 when the lifetime is decreased from 100 to 5 ns. These results clearly demonstrate that the latch-up suppression by reducing the length of the n +-source region as suggested in the proposed latch-up-free IGBT is far more effective than reducing the carrier lifetime.