Latch-up Current Research Articles

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

Overview on Latch-Up Prevention in CMOS Integrated Circuits by Circuit Solutions

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.

Characteristics of latch-up current of dose rate effect by laser simulation

Due to the parasitic PNPN structure, the complementary metal oxide semiconductor (CMOS) integrated circuit may be affected by the latch-up effect, and the latching induced by the transient high dose rate Gamma ray has unique characteristics. In order to explore the complex physical mechanism of the latch-up by transient dose rate effect, in this paper we select the pulsed laser with 1064 nm wavelength as an radiation source to simulate the gamma ray radiation environment, select bulk silicon CMOS deserializer FIN1218MTDX, and use transient dose rate effect laser simulation experiments to explore its latch-up threshold and latch-up current characteristics. The test obtains that the dose rate latch-up threshold optical power density of the device at 3.3 V operating voltage is (8.5 ± 1.2) × 10<sup>4</sup> W/cm<sup>2</sup>, a latch-up voltage of the device is 2.8 V, only the device latches when the supply voltage is greater than 2.8 V. At the same time, it is found that under the working voltages of 3.3 V and 3.6 V and the optical power density between 1.9 × 10<sup>6</sup> W/cm<sup>2</sup> and 1.6 × 10<sup>7</sup> W/cm<sup>2</sup>, the latch-up current significantly decreases, the latch-up current " window phenomenon” appears. Based on the equivalent circuit model, the multi-path latching mechanism is used to construct the HSPICE model. The mechanism of the transient dose rate latching characteristics exposed by the laser test is analyzed by circuit-level simulation. The results show that the latch-up current and the latch-up voltage are related to its own latch structure when the device is latched. The phenomenon of latch-up current window in laser test is due to the multi-path latch mechanism, which will be in the specific circuit structure, and causing the multiple latch-up paths of the device to be switched. The reason of the latch-up path is switched is that the different holding voltages and trigger conditions between the latch-up paths, distributed resistance in the circuit reduces the voltage of latch-up path, so that the holding voltage of the latch-up path cannot be satisfied and the latch-up path is released. At the same time the other latch-up path is latched.

Dual Gate Emitter Switched Thyristor의 Latch-up 전류 특성

Two dimensional MEDICI simulator is used to study the characteristics of latch-up current of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics, latch-up current density, ON-voltage drop and electrical property with the variations of p-base impurity concentrations. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have the better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer p-base structure under the floating <TEX>$N^+$</TEX> emitter indicates to have the better characteristics of latch-up current and breakover voltage.

The characteristics of the lateral IGBT on the thin SOI film when the collector voltage of the IGBT is applied to the substrate

The characteristics of the lateral IGBT on an SOI film when the collector voltage of the IGBT is applied to the substrate are investigated for its application to a high side switch. The measurements of the blocking capability and the dynamic latch-up current during the turn-off transient under an inductive load are carried out with varying thicknesses of the SOI film. A 260 V IGBT can be fabricated on a 5 /spl mu/m thick SOI film without the special device structure. The dynamic latch-up current is improved by reducing the SOI film thickness. This paper shows that applying the collector voltage of the IGBT to the substrate makes it possible to improve the characteristics of the IGBT on a thin SOI film.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Latch-up Suppressed Insulated Gate Bipolar Transistor by the Deep p+ Ion Implantation under the n+ Source

A novel insulated gate bipolar transistor (IGBT) structure, which employs the self aligned deep p+ buried region enveloping all the area under the n+ source, is proposed and verified by SUPREM IV and PISCES-IIB simulation. The simulation results show that the latch-up current is found to increase up to about 10 times compared with the conventional structure when the implantation dose of the p+ buried region and the p-body are 1×1015 cm-2 and 1×1014 cm-2, respectively. The variation of the threshold voltage is within 0.1 V although the implantation dose of the p+ buried region increases from 1×1014 cm-2 to 1×1015 cm-2.

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n/sup +/-p/sup +/ spacing L longer than 8 mu m, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Latch-up DC triggering and holding characteristics of n-well, twin-tub and epitaxial CMOS technologies

The dependence of the latch-up susceptibility on layout parameters is studied on four stripe structures made using different CMOS processes: a standard n-well, a twin-tub and twin-tub epitaxial technology. The correlation between triggering currents, well and substrate resistances and parasitic transistor gains is studied by means of emitter current triggering measurements and two-dimensional simulations using HFIELDS. Triggering currents higher than 250 mA are obtained on epitaxial structures with n+ guard-rings. Anomalies in triggering and holding electrical characteristics are caused by the three-dimensional distribution of the latch-up current, which is observed by IR microscopy. These anomalies can affect results of conventional latch-up testing methods.

Latch-up on CMOS/EPI devices

A dedicated latch-up test system has been developed and was used on two beam lines, the GANIL cyclotron and the IPN Tandem Van de Graaff located in Caen and Orsay (France). The main characteristics of these facilities are presented. Several VLSI circuits were irradiated, and the latchup phenomenon was detected on eight CMOS/EPI devices, revealing various ranges of sensitivity. Recording of the value and rising edge of latchup current was also performed. The problem of whether or not latchup-sensitive circuits should be used for space projects and the need for studies of component design hardening, system design hardening, and latchup rate prediction are addressed. Data are presented on several CMOS/EPI devices demonstrating that an epitaxial layer cannot efficiently achieve latchup immunity for some of the latest technologies. >

Recent advances in insulated gate bipolar transistor technology

Device design of the insulated gate bipolar transistor (IGBT) has been optimized to reduce the distributed transmission-line effect. In addition, cell geometry is chosen to yield high latchup current capability and low forward-voltage drop simultaneously. The vertical structure is optimized to enhance both the turn-off speed and the safe operating area of the IGBTs. The turn-off time of the n-IGBT has been shortened to be as low as 40 ns. The p-channel IGBT latchup current has been improved four to six times over the previously reported results through innovative design and processes. An open-base bipolar transistor model has been implemented to investigate transient IGBT characteristics. >

Infrared microscopy study of anomalous latchup characteristics due to current redistribution in different parasitic paths

Anomalous effects such as abrupt variations of the latchup current in steady-state conditions and window effects, i.e. the existence of a well-defined interval of I/O injected currents for latchup to occur, can occur during pulsed latchup tests. Infrared microscopy allows the correlation of electrical characteristics with latchup current distribution and reveals that anomalous effects are due to the dynamic competition between different latchup paths. This is confirmed by a SPICE simulation of the lumped equivalent circuit of a CMOS output comprising two coupled p-n-p-n parasitic structures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Diffused resistors characteristics at high current density levels-analysis and applications

Both heavily (source-drain) and lightly (well) doped diffused resistors used in modern CMOS integrated-circuit technologies are studied under high current density levels. The effects of high-field mobility degradation, space-charge limited-current, and charge-depletion narrowing (pinchoff) are discussed, and the related analytical solutions are derived and characterized. The applicability of the study to electrostatic discharge (ESD) protection networks, latchup protection circuitry, and output noise suppression resistors is addressed. Velocity saturation due to mobility degradation is found to be the prevailing mechanism, while space-charge limiting current and depletion narrowing have only limited effect on the lightly doped ones. The resulting saturation current densities allow proper resistor designs which can effectively limit ESD and latchup current into highly susceptible nodes and thus-improve overall circuit reliability, potential suppression of I/O switching noise is also discussed and shown to be more sensitive to the ratio between peak noise and steady-state currents. The experimental data confirm the theoretically predicted saturation velocity and critical field for the lightly doped case but show substantial discrepancy for the heavily doped layer. >

An insightful analysis of the hybrid insulated-gate bipolar transistor

The shorted-anode or hybrid insulated-gate bipolar transistor (HIGBT) is examined theoretically (using a first-order analysis) and experimentally (using specially designed test structures) to give physical insight regarding the unique electrical properties of this power switching device. Basic differences between the HIGBT and the conventional lateral IGBT reflected by measurements of on-state conductance, transient turn-off time, and latchup current are explained and shown to be critically dependent on the structural geometry of the device. Also, a previously unacknowledged mode of operation of the HIGBT is demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Three-dimensional distribution of CMOS latch-up current

This paper presents experimental evidence of relevant three-dimensional (3-D) effects in CMOS latch-up obtained by means of novel multicontact test structures. It is also shown that "quasi-" two-dimensional (2-D) experimental data in good agreement with numerical simulations can be achieved only by limiting the analysis to the central sections of wide experimental devices.

A new technique to accurately determine latch-up holding conditions using light excitation

A simple and accurate method to determine the true CMOS latch-up holding current and voltage by avoiding the "quasi-stable" negative resistance region is reported. A combination of microscope light excitation and a low-output impedance programmable power supply permits millivolt resolution, eliminates the need for a series current limiting resistor, and allows automatic testing. Results from test structures fabricated with n-well CMOS process are used to illustrate the method. With the terminal voltage during the excitation only 20-100 mV above the holding voltage, the method is practically nondestructive and therefore especially suitable for characterization of structures with high latch-up currents.

Imaging Latch-up Sites in CMOS Integrated Circuits Using Laser Scanning

A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (IC's) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor.

Cell geometry effect on IGT latch-up

The effect of the emitter cell geometry on insulated gate transistor (IGT) performance has been investigated. The three-dimensional well resistances (emitter shunting resistance) of the square, circular, stripe, and multiple surface short (MSS) have been calculated. The MSS cell geometry has the lowest emitter shunting resistance. As a result, MSS cell has the highest latch-up current capability. It has been experimentally proven that the stripe cell has extremely high latch-up current, and the MSS cell design is current limited. The IGT's with circular and square cell have the lowest latch-up current capability.