Latch-up Phenomenon Research Articles

Investigation of Single-Event Effects for Space Applications: Instrumentation for In-Depth System Monitoring

Ionizing radiation induces the degradation of electronic systems. For memory devices, this phenomenon is often observed as the corruption of the stored data and, in some cases, the occurrence of sudden increases in current consumption during the operation. In this work, we propose enhanced experimental instrumentation to perform in-depth Single-Event Effects (SEE) monitoring and analysis of electronic systems. In particular, we focus on the Single-Event Latch-up (SEL) phenomena in memory devices, in which current monitoring and control are required for testing. To expose the features and function of the proposed instrumentation, we present results for a case study of an SRAM memory that has been used on-board PROBA-V ESA satellite. For this study, we performed experimental campaigns in two different irradiation facilities with protons and heavy ions, demonstrating the instrumentation capabilities, such as synchronization, high sampling rate, fast response time, and flexibility. Using this instrumentation, we could report the cross section for the observed SEEs and further investigate their correlation with the observed current behavior. Notably, it allowed us to identify that 95% of Single-Event Functional Interrupts (SEFIs) were triggered during SEL events.

A 13.56 MHz Low-Power, Single-Stage CMOS Voltage-Boosting Rectifier for Wirelessly Powered Biomedical Implants

In this paper, a low-power, single-stage, active rectifier based on a new charge-pump circuit is presented to be used in biomedical implants. The proposed circuit not only rectifies the AC input voltage to a DC voltage but also amplifies the DC output voltage to a higher level. Low-loss MOS switches are used in the structure of the designed circuit to provide high power conversion efficiency. In addition, by using two comparators, the reverse leakage current is somehow eliminated, resulting in a higher increase in the power efficiency. By tying the source and bulk terminals of the utilized transistors, the body effect problem has been solved, and by connecting the p-substrate to the ground, which is the lowest voltage in the circuit, the latch-up phenomenon is eliminated without any extra circuit. The proposed rectifier is implemented and post-layout simulated in a 0.18 µm standard CMOS technology. According to the simulation results, 1.205 V output DC voltage is achieved from an AC input signal with the peak-to-peak amplitude of 1 V at the operating frequency of 13.56 MHz with a 3 kΩ load resistance. The total active area of the designed circuit is 0.167 mm2 with a maximum power conversion efficiency of 98.2%, output power in the range of 0.5–1.5 mW, and voltage conversion ratio of 120%.

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal–oxide–semiconductor circuits

Gate-grounded n-channel metal–oxide–semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I–V characterization of the GGNMOS used as the power clamp in complementary metal–oxide–semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.

Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor

This study demonstrates an optimal design method for the channel length in a p +–i–p–n + structure of feedback field-effect transistors (FBFETs) for next-generation memory devices. We demonstrate the dependence of latch-up and threshold voltages on the channel length in single-gated FBFETs with silicon channels consisting of gated and non-gated regions. The operation principle of the latch-up phenomena related to the channel length using an equivalent circuit in an FBFET has been described. The abrupt increase in the drain current of the single-gated FBFETs at the latch-up (threshold) voltage in the sweep of the drain (gate) voltage was analyzed with current gains in an equivalent circuit. The current gain depends on the gated and non-gated channel lengths; thereby, the latch-up and threshold voltages too depend on the gated and non-gated channel lengths. The dependences of the latch-up and threshold voltages on the non-gated channel length were found to be 3.62 times and 1.68 times higher than that on the gated channel length, respectively.

Integrate-and-Fire Neuron Circuit Without External Bias Voltages.

In this study, we propose an integrate-and-fire (I&F) neuron circuit using a p-n-p-n diode that utilizes a latch-up phenomenon and investigate the I&F operation without external bias voltages using mixed-mode technology computer-aided design (TCAD) simulations. The neuron circuit composed of one p-n-p-n diode, three MOSFETs, and a capacitor operates with no external bias lines, and its I&F operation has an energy consumption of 0.59 fJ with an energy efficiency of 96.3% per spike. The presented neuron circuit is superior in terms of structural simplicity, number of external bias lines, and energy efficiency in comparison with that constructed with only MOSFETs. Moreover, the neuron circuit exhibits the features of controlling the firing frequency through the amplitude and time width of the synaptic pulse despite of the reduced number of the components and no external bias lines.

Contrast of latch-up induced by pulsed gamma rays in CMOS circuits after neutron irradiation and TID accumulation

We investigate the difference in the probability of latch-up occurrence in complementary metal–oxide–silicon (CMOS) circuits exposed to neutron radiation and total ionizing dose (TID), which are subsequently exposed to pulsed gamma rays. First, we irradiate three types of CMOS circuits in a reactor for neutron exposure and in a Co-60 unit for TID exposure respectively, which are then placed in a pulsed gamma-ray environment. The latch-up induced by pulsed gamma-ray irradiation is studied. Our experimental results indicate that the manifestation of the latch-up phenomenon is different among the devices after neutron irradiation and TID exposure, thereby indicating that the influences of neutron and TID exposures on the latch-up sensitivity are different. To understand how the latch-up sensitivity changes, we study a dynamic model for latch-up occurrence and analyse the influences of neutron and TID exposure using the model. Our results indicate that neutron injection reduces the susceptibility of latch-up occurrence, whereas TID exposure increases the latch-up occurrence susceptibility. Therefore, in the case of CMOS circuits exposed to pulsed gamma-ray irradiation, the latch-up threshold decreases with TID accumulation, but increases with neutron fluence augmentation. Interestingly, the latch-up threshold drops when the neutron fluence is sufficiently large, mainly because concomitant gamma rays in the reactor environment play an important role in affecting the threshold.

Total ionizing dose induced single transistor latchup in 130-nm PDSOI input/output NMOSFETs**Project supported by Shanghai Municipal Natural Science Foundation, China (Grant No. 15ZR1447100).

Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator (PDSOI) NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly correlates with the bias configuration during irradiation. It is found that the high body doping concentration can make the devices less sensitive to the single transistor latchup effect, and the onset drain voltage at which latchup occurs can degrade as the total dose level rises. The mechanism of band-to-band tunneling (BBT) has been discussed. Two-dimensional simulations were conducted to evaluate the BBT effect. It is demonstrated that BBT combined with the positive trapped charge in the buried oxide (BOX) contributes a lot to the latchup effect.

Mechanism of multiple bit upsets induced by localized latch-up effect in 90 nm complementary metal semiconductor static random-access memory

By using the pulsed laser single effect facility, the single event upset and latch-up phenomenon are studied, and the bitmap of 90 nm complementary metal oxide semiconductor (CMOS) static random-access memory (SRAM) is mapped. It is shown that many multiple bit upsets occur and pulsed supply current of 20 mA amplitude is monitored. Based on the technology computer aided design (TCAD), it is found that the localized latch-up in CMOS SRAM is the main reason for the single event multiple bit upsets. Finally, by analyzing the results of the pulsed laser experiment and TCAD, it is found that the P/N well potential collapse is the key physical mechanism responsible for the spreading of the single event latch-up effect in 90 nm CMOS SRAM.

New Approach for Transient Radiation SPICE Model of CMOS Circuit

Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

과도방사선에 의한 CMOS 소자 Latch-up 모델 연구

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit.. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

Photoelectric Laser Stimulation applied to Latch-Up phenomenon and localization of parasitic transistors in an industrial failure analysis laboratory

This paper describes a new technique that uses a 1064nm wavelength laser for failure analysis of CMOS integrated circuits. We propose a new flow to deal with Latch-Up (LU) phenomenon issues and for this we have developed a new technique that allows localizing areas sources of Latch-Up triggering in an Integrated Circuit (IC). An effectiveness of this method is verified by an experiment on a microcontroller and has proved to be useful for finding the sensitive location. The proposed methodology further extends the capabilities of Photoelectric Laser Stimulation (PLS) in qualification and characterization domains.

A Study on PCB's Latch-up Phenomenon by External Electrical Surge

There are many cases that interrupt the production process because of malfunctions caused by electronic circuit boards which control equipment, but it is difficult to distinctly identify the causes in many cases. Especially, CMOS devices with the control logic circuit return automatically to normal state after their own faults. Therefore it is not easy to analyze the problems with electronic circuit boards. Recently, nuclear power plant experienced a failure due to the malfunction of electronic circuit boards and it was identified that the reason of the malfunction was because of latch-up phenomenon caused by external surge in electronic devices. This paper presents the causes and the phenomenon of latch-up by experiment and also a way using counter EMF diodes, noise filters and surge protective devices to prevent latch-up phenomenon from electronic circuit boards, finally confirms the effectiveness of the result by experiment.

Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology

Substrate current distribution as trigger for external latch-up (LU) and transient latch-up (TLU) is analyzed by optical transient interferometric mapping (TIM) technique. The transient free carrier (plasma) concentration related to substrate current flow is studied for various guard-ring configurations and injection carrier type on special test structures and real I/O cells. TIM uncovers proximity effects in I/O cells causing substrate current crowding which are important for the definition of effective LU protection concepts.

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Forward body biasing is a promising approach for realizing optimum threshold-voltage <formula formulatype="inline"><tex Notation="TeX">$(V_{\rm TH})$</tex></formula> scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias <formula formulatype="inline"><tex Notation="TeX">$(V_{F})$</tex></formula> decreases the depletion width <formula formulatype="inline"><tex Notation="TeX">$(X_{\rm DEP})$</tex></formula> in the channel region, it reduces <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small <formula formulatype="inline"><tex Notation="TeX">$X_{\rm DEP}$</tex> </formula>) at low <formula formulatype="inline"><tex Notation="TeX">$V_{\rm TH}$</tex></formula> notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for <formula formulatype="inline"><tex Notation="TeX">$\vert V_{F}\vert$</tex></formula> should be set at 0.6–0.7 V, which is sufficient to realize significant advantages of forward body biasing. </para>

Silicon-on-insulator for high-temperature applications

The silicon-on-insulator (SOI) CMOS technology is one of the best candidates for high-temperature applications due to its low leakage current, steep subthreshold slope, absence of latch-up phenomenon and temperature-resistant threshold voltage. However, the most critical elements for high temperature applications are transmission lines, especially thin-film microstrip lines. In the paper, the impact of high-temperature operation on the RF performance of some SOI circuits is analysed up to 250 degrees C.

Field failure mechanism and improvement of EOS failure of integrated IGBT inverter modules

In this paper, we have proved that the soft damage from human body ESD can actually cause EOS damage, while integrated IGBT inverter modules (or intelligent power modules) are operating. Failure mechanism was defined as a latchup phenomenon by ESD damage leakage. Failure modes of each failed IGBT inside two integrated IGBT inverter modules were soft and hard burnout, respectively. To determine the failure mechanism, we have done fault tree analysis. From this analysis, we could conclude the main factor as the ESD event between device ESD immunity and PCB assembly line. In addition, from the PCB assembly line, we have identified damage samples due to an ESD event. Based on this result, we have implied ESD on IGBT and intentionally caused a leakage, then applied the device to the system. After an aging test, we could reproduce soft burnout and hard burnout.

Transient-induced latch-up test setup for wafer-level and package-level

Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests, like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail to identify this susceptibility. The presented test method and setup allows to study the transient induced latch-up (TLU) phenomenon employing nstrigger impulses at wafer-level and package-level. A TLU-module superimposes the DC voltage of the power supply with a short stress pulse and delivers the combination to the tested pin of the DUT, avoiding destructive EOS. Closest possible distances between the TLU-module and the DUT and the use of RF-probes at wafer level allow risetimes of less than 1 ns, time resolved measurements of voltage and current, and an almost instantaneous limitation of the supply current after latch-up has been triggered. The short stress pulses were generated by transmission lines or solid state pulse generators. Abrupt changes in the voltage and current amplitudes indicate that latch-up has been triggered. The method is successfully demonstrated for several devices in different technologies.

Local and pseudo SELs observed in digital LSIs and their implication to SEL test method

The characteristic nondestructive single-event latchup (SEL) phenomena, "local" and "pseudo" SELs, were identified in complex digital Large Scale Integrations (LSIs) by using a photo-emission microscope. Usually, SELs are detected as an abrupt increase of power supply current. However, it was experimentally demonstrated that the simple method could not give sufficient information to determine if it is a destructive or a nondestructive phenomenon. If the observed SELs can be confirmed as a nondestructive phenomenon with a certain confidence level, a simple circumvention technique can be effectively employed and the chance to utilize attractive commercial devices will be greatly enhanced. The SEL test method to identify this type of LSI was discussed and a new procedure was proposed.

Stress Mechanism about Field Lightning Surge of High Voltage BJT Based Line Driver for ADSL System

In this paper, we have verified stress root caused by lightning surge in High voltage BJT based line driver of ADSL telecommunication and created failure mechanism. To reproduce damages in Line driver, we have applied STD surge waveform in operating condition, which is specified in IEC-6000-4-5, to component and board level. Visual isolation for Damage root was conducted with Real-time Electrical Stress Analysis (RTESA) utilizing Photon Emission Microscopy (PEM). The surge made with input of Tx output created junction breakdown of amplifier, which is made of HVBJT cells, and also caused current crowding from Vcc (supply voltage). In case of Positive pulse, current crowding was observed from between Collector and Vcc (+)12V. For negative pulse, at between Emitter and Vee (−)12V, current crowding was found. For both cases, device damage level was the same. All of these could be considered as transient latchup phenomenon created in BJT cell. Applying temporary clamping diode to line driver Tx, we have conducted Board level surge injection test. As a result, with the correlation between surge level from component level reproduction test and the one from system level, we have decided field lightning surge damage level and set up line driver protection margin.

Latchup in voltage tolerant circuits: a new phenomenon

The semiconductor industry relies on latchup testing of integrated circuits (ICs) to detect and prevent catastrophic failures under extreme conditions. The test is mandatory to ensure that parasitic components do not adversely affect the normal behavior of the ICs, especially in CMOS technologies. This phenomenon has been well documented over the years. For the newer technologies with lower power consumption (supplies in the range of 1–2 V), one might consider them to be less susceptible to latchup. However, the presently designed ICs with nanometer technologies continue to require “high voltage” interface compatibility through applications such as PCI, etc. Moreover, some of the IC pins are exposed to much higher level ESD stresses (IEC test) due to pin connections between systems. As a consequence, latchup has become more difficult while manifesting itself into new scenarios including system level ESD effects.This paper first reviews the background of the latchup phenomenon and then introduces a new form of latchup called Signal Latchup that could very well be a critical issue for the newer IC applications where high voltage compatibility is required. In this same context, System Level ESD latchup is also described. This paper gives the background of CMOS latchup, followed by a description of the latchup initiation and latchup immunity test methods. The system board reliability is discussed. The new Signal Latchup phenomenon is introduced. An illustration of Signal Latchup occurring in voltage tolerant circuits and the design improvement to overcome this are presented in detail. The impact of process technology on these new latchup effects is evaluated and the system ESD latchup is presented. The Signal Latchup and ESD system Latchup testing is covered. Finally, the conclusions are given.