Event Latchup Research Articles

EXPERIMENTAL STUDY AND SPICE SIMULATION OF CMOS INVERTERS LATCH-UP EFFECTS DUE TO HIGH POWER MICROWAVE INTERFERENCE

Experimental study and SPICE simulation of CMOS digital circuits latch-up effects due to high power microwave interference are reported in this paper. As a traditional inherent destruction phenomenon, latch-up effect may jeopardize the correct function of the circuits, and could be triggered in various ways such as ESD pulse, cosmic ray, heavy ion particles etc. Through the directly injected experimental investigation of CMOS inverters, it is shown that the single short high power RF pulse not only could disturb and upset the inverters output logic voltage, but also might trigger CMOS latch-up effects. It is observed that the RF pulse leading to inverters latch-up effects have energy threshold characteristics, which means that the injected RF pulse power is inversely proportional to the pulse width. SPICE simulations indicated that the inverters maximum static consumption current in latch-up state will increase up to 6600 multiples compared to the normal value when input logic state is high. With the device scaling down, higher integration and higher working frequency, the power consumption problem plays a significant role, which makes CMOS logic circuits more vulnerable due to the latch-up effects under high power microwave threats.

Evaluation of OKI SOI technology

The silicon-on-insulator (SOI) CMOS technology has a number of advantages over the standard bulk CMOS technology, such as no latch-up effect, high speed and low power. The fully depleted SOI (FD-SOI) technology provided by OKI Electric Industry Co., Ltd. is realizing the full features of the advantages with lowest junction capacitance. Test element group (TEG) structures of transistors were fabricated and irradiated with protons. The first results are presented.

Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up

Current flow uniformity during ESD induced latch-up event is investigated in multi-finger LDMOS clamps and SCR ESD protection devices fabricated in a 0.6 μm high voltage CMOS process. Current flow, excess free carrier and hot spot distribution are analyzed by transient interferometric mapping technique combined with a latch-up pulse system consisting of a solid state pulser and a clear pulse unit. During latch-up, the current in the LDMOS clamps flows just in a single spot and the failure position is random and independent on device type. The position of the failure site correlates with the trigger position of the device. The SCRs exhibit pulse-to-pulse instabilities in the current flow.

Particle detector prototype based on a discrete cell sensitive to the latchup effect

The paper describes an innovative idea for an ionizing particle detector. The principle is based on a latchup effect that is common in to-date CMOS technologies working in a radiation environment. In principle the detector can operate at room temperature, does not require a high voltage power supply and is intrinsically more tolerant to radiation effects than the common solid-state detectors. A latchup-based detector can be constructed using state-of-the-art technologies and could be applied for beam monitoring or as a heavy-ion selector. A prototype made up of discrete components is described and its rough sensitivity is exploited. Tests with daylight, electrons, via a current pulse generator and with a laser beam have proved that charge sensitivity of the order of 1 pC can be easily achieved.

A 0.8 V CMOS amplifier design

A low-voltage operational amplifier design in a standard CMOS process is presented for operation at ±0.4 V. The design incorporates a low voltage level shift current mirror using forward body-biased MOSFETs limited to a maximum of 0.4 V to minimize latchup and hot carrier effects. Some of the measured performances are as follows: 58 dB open-loop gain, 30 kHz bandwidth, 50° phase margin and 80 ?W power dissipation and are in close agreement with the corresponding design and SPICE simulated values.

Catastrophic latchup in a CMOS operational amplifier

We report catastrophic single-event latchup results for a CMOS operational amplifier. Thermal and optical imagings in conjunction with current distributions were used to identify latchup-sensitive regions. Differences in cross section for various ions show that charge is collected at depths beyond 40 /spl mu/m, causing the cross section to be underestimated unless long-range ions are used. Latchup testing with short-range ions may underestimate the cross section or even fail to trigger a latchup event that would occur with more energetic ions.

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work. The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and p-substrate to be a triggering source of the latchup occurrence in this IC. The parasitic diode of the internal PMOS was easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR) path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been also proposed in this paper.

Proposal for solid-state particle detector based on latchup effect

A novel approach to detect particles by means of a solid-state device susceptible to latchup effects is described. The stimulated ignition of latchup effects caused by external radiation has so far proven to be a hidden hazard. This is proposed as a powerful means of achieving the precise detection and positioning of a broad range of particles with a spatial resolution of 5 µm.

Latchup in voltage tolerant circuits: a new phenomenon

The semiconductor industry relies on latchup testing of integrated circuits (ICs) to detect and prevent catastrophic failures under extreme conditions. The test is mandatory to ensure that parasitic components do not adversely affect the normal behavior of the ICs, especially in CMOS technologies. This phenomenon has been well documented over the years. For the newer technologies with lower power consumption (supplies in the range of 1–2 V), one might consider them to be less susceptible to latchup. However, the presently designed ICs with nanometer technologies continue to require “high voltage” interface compatibility through applications such as PCI, etc. Moreover, some of the IC pins are exposed to much higher level ESD stresses (IEC test) due to pin connections between systems. As a consequence, latchup has become more difficult while manifesting itself into new scenarios including system level ESD effects.This paper first reviews the background of the latchup phenomenon and then introduces a new form of latchup called Signal Latchup that could very well be a critical issue for the newer IC applications where high voltage compatibility is required. In this same context, System Level ESD latchup is also described. This paper gives the background of CMOS latchup, followed by a description of the latchup initiation and latchup immunity test methods. The system board reliability is discussed. The new Signal Latchup phenomenon is introduced. An illustration of Signal Latchup occurring in voltage tolerant circuits and the design improvement to overcome this are presented in detail. The impact of process technology on these new latchup effects is evaluated and the system ESD latchup is presented. The Signal Latchup and ESD system Latchup testing is covered. Finally, the conclusions are given.

The radiation sensitivity mapping of ICs using an IR pulsed laser system

Recent results obtained with a pulsed nanosecond IR laser system to automatically test single event latch-up effects in laboratory are presented. In particular, the capabilities of this system to perform detailed mapping for ICs sensitivity to radiation are discussed. Two VLSI ASIC circuits were used for sensitivity mapping. The results are compared with those obtained in heavy ion tests at GSI (Darmstad, Germany).

Magneto-optical observation of the latchup effect in CMOS ICs induced by uniform and local irradiation

A new application of garnet films with high Faraday rotation—the first direct observation of latchup effect in serially produced complementary metal-oxide-semiconductor integrated circuits (CMOS ICs)—is reported. The visualization method based on the formation of straight domain walls inside magneto-optical films along electrical current path in ICs is used. The influence of spatially uniform or focused laser irradiation on the latchup configuration and thresholds is discussed.

Catastrophic latchup in CMOS analog-to-digital converters

Heavy-ion latchup is investigated for analog-to-digital converters. Differences in cross section for various ions show that charge is collected at depths beyond 50 /spl mu/m, causing the cross section to be underestimated unless long-range ions are used. Current distributions, thermal imaging, and diagnostic tests with a pulsed laser were used to identify latchup-sensitive regions. Latchup in one of the circuit types was catastrophic, even when the power was turned off within 2 ms of a latchup event. Examination of damaged devices with a scanning electron microscope showed that the failures occurred in metallization and contact regions. Current density for failure agrees with pulsed current metallization stress data in the literature.

Magneto-optical observation of surface currents in microelectronic circuits

A magneto-optical method is applied to observe surface electrical currents in microelectronic devices. We describe here the opportunity of direct experimental localization of latchup effect in complementary metal-oxide-semiconductor integrated circuits (ICs) by visualization of latchup current path in surface layer of ICs substrate. To observe currents greater than 10 mA the garnet films with both uniaxial and in-plane anisotropy are utilized. Optimal polarization geometry providing maximal visual contrast is calculated. Topologies of both solitary and two neighboring electrical currents are experimentally investigated. The sensitivity limit (minimal current surface density) of this method of magneto-optic visualization is estimated to be 0.1 mA/μm.

Building in reliability with latch-up, ESD and hot carrier effects on 0.25 μm CMOS technology

In this study, three major reliability aspects, hot carrier effects, latch-up and electrostatic discharge (ESD) have been simultaneously studied on a 0.25 μm complementary metal-oxide silicon (CMOS) technology. For this purpose, three source–drain architectures large angle tilted implementation drain (LATID, MDD, Abrupt) processed on different kinds of substrate (bulk and epitaxial ones) are compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source–drain architecture affects, of course, the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective in reducing latch-up occurrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various reliability aspects.

Ion induced charge collection and SEU sensitivity of emitter coupled logic (ECL) devices

This paper presents single event upset (SEU) and latchup test results for selected Emitter Coupled Logic (ECL) microcircuits, including several types of low capacity SRAMs and other memory devices. The high speed of ECL memory devices makes them attractive for use in space applications. However, the emitter coupled transistor design increases susceptibility to radiation induced functional errors, especially SEU, because the transistors are not saturated, unlike the transistors in a CMOS device. Charge collection at the sensitive nodes in ECL memory elements differs accordingly. These differences are responsible, in part, for the heightened SEU vulnerability of ECL memory devices relative to their CMOS counterparts.

Analysis of latchup and parasitic effects in merged BiCMOS structures

Latchup and performance degradation due to the parasitic elements in merged BiCMOS structures are studied. Circuit simulations using HSPICE and analytical characterisation are used to describe the parasitic components and model their effects on the output voltage switching characteristics and delay time. A latchup factor is defined to relate the degree of performance degradation to the device and key circuit parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Matrix method for latch-up free demonstration in a triple-well bulk-silicon technology

A CMOS inverter made in bulk silicon by triple-well technology is examined with respect to its latch-up behavior. With this exemplary circuit and a matrix-like scheme it can be proved that the conditions for the occurrence of the latch-up effect are not met in any case. It is demonstrated that this type of technology leads to completely latch-up free CMOS circuits in bulk silicon and, therefore, extremely good hardness against transient radiation induced effects can be achieved without using SOI (silicon on insulator) and SOS (silicon on sapphire). Improved insensitivity to SEU (single event upset) can be expected. The existing paths between any of the distinguishable regions do not meet the requirements for the occurrence of latch-up.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analysis of d.c. and a.c. anomalous latch-up effects in commercial CMOS integrated circuits

Anomalous effects in electrical latch-up characteristics have been identified both in the d.c. (hysteresis effects) and a.c. (window effects) characteristics of a large sample of commercial CMOS ICs of different suppliers and technologies. Both d.c. and a.c. effects were always present in all tested devices which showed anomalies. Infra-red microscopy and scanning laser microscopy reveal that both effects are caused by current redistribution between different latch-up paths and are therefore correlated.

The influence of the measurement setup on enhanced AC hot carrier degradation of MOSFETs

It is shown that the enhanced degradation and substrate current component, which is observed in several AC experiments at the falling edge of the gate pulse under high drain bias, can in some cases be primarily ascribed to a carrier injection due to the forward biasing of the source diode and a simultaneous drain voltage overshoot. The forward biasing of the source diode is not caused by the commonly known latch-up effect, which is triggered by the substrate current, but by an insufficient AC coupling of the source to the ground due to the parasitic inductance of the wiring. It is demonstrated that by putting a capacitor at the drain side of the transistor and grounding the source at the probe tip, the observed enhanced substrate current can be eliminated and the anomalous enhanced degradation reduced accordingly. >

Analysis of latch-up neighborhood effects in VLSI CMOS input and output stages

The influence of electron and hole injection from neighboring structures on the latch-up hardness of an inverter in non-epitaxial CMOS is measured on specially designed test structures and compared with the results of two-dimensional numerical simulation provided by the program BAMBI. An analysis of the basic effects is given and remedial measures to avoid neighborhood effects are described.