Event Latchup Research Articles

Evaluation of sensitivity parameters for single event latchup effect in CMOS LSI ICs by pulsed laser backside irradiation tests

The results of computation-experimental modeling of single-event latchup effects under the laser radiation focused on the IC crystal backside—the substrate side—are presented. Possibilities of applying the technique of local laser irradiation to evaluate equivalent linear energy transfer of heavy ions in the case of the laser irradiation from the substrate side of IC crystal are analyzed. The experimental results obtained using the pulsed laser installation and accelerators of charged particles for a series of modern LSI ICs are compared.

NIR Microscopy Possibilities for the Visualization of Silicon Microelectronic Structure Topology through the Substrate

Experimental setup based on visible and NIR spectral range microscope with laser port and picosecond laser is developed for silicon integrated circuit (IC) failure analysis. The possibility of visualizing the topology of the submicron technology silicon structures from the back side of the crystal through the substrate is shown. Main features of new setup are demonstrated by some results of backside focused pulsed laser beam initiated latchup effect study. The possibility of the localization of the latchup sensitive areas under focused laser irradiation is shown. NIR light emission accompanying the latchup effect is observed and analyzed. The practical aspects of NIR microscopy for failure analysis under backside laser irradiation are discussed.

Development of a radiation-hardened SRAM with EDAC algorithm for fast readout CMOS pixel sensors for charged particle tracking

CMOS pixel sensors (CPS) are attractive for use in the innermost particle detectors for charged particle tracking due to their good trade-off between spatial resolution, material budget, radiation hardness, and readout speed. With the requirements of high readout speed and high radiation hardness to total ionizing dose (TID) for particle tracking, fast readout CPS are composed by integrating a data compression block and two SRAM IP cores. However, the radiation hardness of the SRAM IP cores is not as high as that of the other parts in CPS, and thus the radiation hardness of the whole CPS chip is lowered. Especially, when CPS are migrated into 0.18-μm processes, the single event upset (SEU) effects should be also considered besides TID and single event latchup (SEL) effects. This paper presents a radiation-hardened SRAM with enhanced radiation hardness to SEU. An error detection and correction (EDAC) algorithm and a bit-interleaving storage strategy are adopted in the design. The prototype design has been fabricated in a 0.18-μm process. The area of the new SRAM is increased 1.6 times as compared with a non-radiation-hardened SRAM due to the integration of EDAC algorithm and the adoption of radiation hardened layout. The access time is increased from 5 ns to 8 ns due to the integration of EDAC algorithm. The test results indicate that the design satisfy requirements of CPS for charged particle tracking.

Single-Event Cluster Multibit Upsets Due to Localized Latch-Up in a 90 nm COTS SRAM Containing SEL Mitigation Design

We report a study on a COTS 90 nm low-power SRAM chip, which is immune to single-event latch-up due to its on-chip latch-up suppression circuit. However, under heavy-ion as well as proton irradiation test, the chip exhibits cluster flips, i.e. flipping of tens of bits due to a single particle strike. We attribute the cluster flips to localized latch-up events that can affect a segment of 32 × 64 bits, which is supported by TCAD simulations. We suggest to further scrutinize the latch-up suppression design, due to its apparent inability to prevent localized latch-ups.

Temperature dependence of latch-up effects in CMOS inverter induced by high power microwave

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave (HPM) is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS inverters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.

Mechanism of multiple bit upsets induced by localized latch-up effect in 90 nm complementary metal semiconductor static random-access memory

By using the pulsed laser single effect facility, the single event upset and latch-up phenomenon are studied, and the bitmap of 90 nm complementary metal oxide semiconductor (CMOS) static random-access memory (SRAM) is mapped. It is shown that many multiple bit upsets occur and pulsed supply current of 20 mA amplitude is monitored. Based on the technology computer aided design (TCAD), it is found that the localized latch-up in CMOS SRAM is the main reason for the single event multiple bit upsets. Finally, by analyzing the results of the pulsed laser experiment and TCAD, it is found that the P/N well potential collapse is the key physical mechanism responsible for the spreading of the single event latch-up effect in 90 nm CMOS SRAM.

Single event latch-up effect and mitigation technique in different sized CMOS devices

Single event latch-up effect and mitigation technique in different sized CMOS devices

不同工艺尺寸CMOS器件单粒子闩锁效应及其防护方法

不同工艺尺寸CMOS器件单粒子闩锁效应及其防护方法

Understanding and modeling of internal transient latch-up susceptibility in CMOS inverters due to microwave pulses

This paper analyzes the dependencies of the latch-up sensitivity of the CMOS inverter on the pulse width and the pulse repetition frequency (PRF) of the microwave pulse. Two physics-based models are presented to investigate the microwave pulse triggered latch-up effect and allow IC designers to identify the worst-case testing condition with the combination of the pulse width and the PRF. In model derivation, the continuity equation for electrons is solved with different boundary conditions for the excitation of a single shot microwave pulse and the repetitive microwave pulses, respectively. Device simulation and experimental data reported in literature have been used to verify the validity of these two analytical models. The theoretical model for the effects of pulse width shows that the latch-up sensitivity is an increasing function of the pulse width on a shorter time scale. If the pulse width increases steadily, the latch-up sensitivity becomes independent of the pulse width on a time scale of hundreds of nanoseconds. On the other hand, the theoretical model for the effects of PRF indicates that the latch-up sensitivity is also an increasing function of the PRF and the number of pulses, only if the PRF is far greater than the reciprocal of the minority carrier lifetime. Otherwise, the latch-up sensitivity is insensitive to the PRF or the number of pulses.

Device simulation studies on latch-up effects in CMOS inverters induced by microwave pulse

This paper presents the simulated results of latch-up induced by microwave pulse with respect to pulse parameters, bias voltages and pulse injection conditions. A semi-empirical theoretical model based on the simulated results to access the pulse width and frequency effects on inducing latch-up quantitatively was proposed and agreed with the experimental results reported in the literature. Simulated results also indicated that pulse repetition frequency (PRF) must be far greater than the reciprocal of the minority carrier lifetime to lower the power threshold causing latch-up. Furthermore, excess carrier effects were believed to the primary reason of latch-up and be attributed to the difference between microwave pulse injection conditions.

An Optimization Design in the HV nLDMOS by Taguchi Method

This paper applied the Taguchi method to simulate the latch-up effect of nLDMOS to achieve an optimization design. The applied model is for an nLDMOS structure with high voltage well plus the adaptive (adjustment) layers of source & drain, and an N-type buried layer. Although the methods we could choose is abundant, we hope to effectively obtain the data which is useful for statistics in order to judge the correct characteristic of parameters. We applied the Taguchi method to perform an optimization in the paper. There are six parameters with two levels in this work, so we choose the Taguchi table to be L8(27). By this way, it can decrease the times of experiment much effectively.

Application of transient interferometric mapping method for ESD and latch-up analysis

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.

Turn-off Time as a Precursor for Gate Bipolar Transistor Latch-up Faults in Electric Motor Drives

In this paper, effects preceding a latch-up fault in insulated gate bipolar transistors (IGBTs) are studied as they manifest within an electric motor drive system. Primary failure modes associated with IGBT latch-up faults are reviewed. Precursors to latch-up, primarily an increase in turn-off time and junction temperature, are examined for the IGBT. In addition, the relationship between junction temperature and turn-off time is explained by examining the semiconductor properties of an IGBT. To evaluate the effects preceding latch-up, seeded fault testing is conducted using aged transistors induced with a fault located in the die-attach solder layer. Since junction temperature cannot be directly measured, the transistor turn-off time is used as a measured system parameter to correlate between healthy and fault conditions. The experimental results provide statistically significant evidence (within 99% confidence) that an IGBT latchup event, caused by elevated junction temperatures, can be detected by monitoring the transistor turn-off time insitu.

A Circuit-Level Substrate Current Model for Smart-Power ICs

This paper presents a new modeling methodology accounting for generation and propagation of minority carriers that can be used directly in circuit-level simulators in order to estimate coupled parasitic currents. The method is based on a new compact model of basic components (p-n junction and resistance) and takes into account minority carriers at the boundary. An equivalent circuit schematic of the substrate is built by identifying these basic elements in the substrate and interconnecting them. Parasitic effects such as bipolar or latch-up effects result from the continuity of minority carriers guaranteed by the components’ models. A structure similar to a half-bridge perturbing sensitive n-wells has been simulated. It is composed by four p-n junctions connected together by their common p-doped sides. The results are in good agreement with those obtained from physical device simulations.

Latchup Topology for Pixel Readout Using Commercial Transistors

The stimulated ignition of latchup effects caused by external radiation has till now proved to be a hidden hazard. However this paper presents the effect in a new light-as a new approach for detecting particles by means of a solid-state device susceptible to latchup effects. This device can also be used as a circuit for reading a sensor's signal by leaving off-circuit sensing capabilities. Given that MOS transistors are widely used in microelectronics devices and sensors, the latchup-based cell is proposed as a new structure for future applications in particle detection, in the amplification of sensor signals and also in radiation monitoring.

Feasibility study of a latchup-based particle detector exploiting commercial CMOS technologies

The stimulated ignition of latchup effects caused by external radiation has so far proved to be a hidden hazard. Here this effect is described as a novel approach to detect particles by means of a solid-state device susceptible to latchup effects. In addition, the device can also be used as a circuit for reading sensors devices, leaving the capability of sensing to external sensors. The paper first describes the state-of-the-art of the project and its development over the latest years, then the present and future studies are proposed. An elementary cell composed of two transistors connected in a thyristor structure is shown. The study begins using traditional bipolar transistors since the latchup effect is originated as a parasitic circuit composed of such devices. Then, an equivalent circuit built up of MOS transistors is exploited, resulting an even more promising and challenging configuration than that obtained via bipolar transistors. As the MOS transistors are widely used at present in microelectronics devices and sensors, a latchup-based cell is proposed as a novel structure for future applications in particle detection, amplification of signal sensors and radiation monitoring.

Novel approaches to radiation detection and readout using the latch up effect

An alternative topology for solid-state pixel detectors is described. It is based on latch-up effect, usually exploited in solid-state electronic switches like thyristor and Silicon Controlled Rectifiers (SCRs). It is proposed here to use this effect as a simple building-block element for particle and radiation detection. Review of the latch-up effect and description of circuit topologies under investigation to assess the operating principle and initial experimental results will be presented. Applications in particle and radiation detection will be suggested.

Investigation of Minority Carrier Distribution in Semiconductor-Controlled Rectifier Devices and the Impact on Electrostatic Discharge Applications

In this paper, a physical mechanism is proposed where the holding voltage of the semiconductor-controlled rectifier (SCR) is predominated by the accumulation of minority carriers. Two-dimensional simulation is used to demonstrate this mechanism where the carrier distribution of SCR devices is calculated and analyzed. It has been clearly proven that the distribution of minority carriers highly correlates to holding voltage. Accordingly, a layout approach has also been designed and experiments have confirmed that an increment in holding voltage can be performed. It can be concluded that the optimization of the topological structure will markedly increase holding voltage and eventually prevent the complementary metal–oxide–semiconductor (CMOS) integration circuit from minimizing the latch-up effect. Moreover, because of its high current capabilities, the optimized SCR can be used as an ideal candidate for electrostatic discharge protection (ESD) applications.

Analysis, design, and implementation of a high-efficiency full-wave rectifier in standard CMOS technology

In this paper we present analysis, design, and implementation of a high-efficiency active full-wave rectifier in standard CMOS technology. The rectifier takes advantage of the dynamic voltage control of its separated n-well regions, where the main rectifying PMOS elements have been implemented in order to eliminate latch-up and body effect. To minimize rectifier dropout and improve AC---DC power conversion efficiency (PCE), all the MOSFET switching elements have been pushed into deep triode region to minimize their resistance along the main current path during conduction. A prototype rectifier was implemented in the AMI 0.5-μm 3M/2P n-well CMOS process. An input sinusoid of 5 V peak at 0.5 MHz produced 4.36 V DC output across a $$1\,\hbox{k}\Upomega\Vert 1\,\mu\hbox{F}$$ load, resulting in a measured PCE of 84.8%.

Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference

Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5 dB m of pulsed interference at frequencies of 1.23 GHz and 4 GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4 GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8 kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25 mA, respectively.