Latch Design Research Articles

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications

High-Performance Latch Designs of Double-Node-Upset Self-Recovery and Triple-Node-Upset Tolerance for Aerospace Applications

Radiation-hardened latch design with triple-node-upset recoverability

As CMOS technology scales down the susceptibility of integrated circuits to radiation effects makes them vulnerable to single-event upsets (SEUs) that may cause the formation of soft errors. In nanometer technologies, SEUs have the potential to impact many nodes within a circuit, resulting to Multiple Node Upsets (MNUs). Several techniques have been proposed to deal with SEUs that simultaneously influence either one, two, or three nodes. This paper presents a latch design that is capable of tolerating up to triple-node upsets (TNUs). Hardware redundancy is exploited to store data in many nodes inside the latch, along with a multiple feedback scheme that provides the recovery of the correct latch state in the case of SEUs. The proposed method provides faster recovery time after an SEU, and at the same time reduced power-delay and area-power-delay products with respect to existing solutions in the literature.

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

With the continuous reduction of feature size of transistors, single-event triple-node-upsets (TNUs) induced by the striking of radiation particles in nano-scale CMOS circuits have emerged as a significant reliability concern. To address the shortcomings of existing radiation-hardened designs, including low reliability and high overhead, this paper proposes a cost-effective and highly robust TNU self-recovery latch design called DOCTRL. The proposed DOCTRL latch primarily consists of six dual-output C-elements (DOCs) and two clocked DOCs. By utilizing DOCs with two independent outputs, the proposed DOCTRL latch achieves a smaller area overhead. In addition, a four-level circular interlock matrix connection is designed to recover all possible TNUs within the proposed DOCTRL latch. Meanwhile, the latch also incorporates clock gating technology and a high-speed path to minimize power consumption and delay penalties. Simulation results indicate that the proposed DOCTRL reduces area by an average of 32.43 %, power consumption by 46.84 %, delay by 14.43 %, and area-power-delay product (APDP) by 69.55 %, compared to the five typical TNU self-recovery latches (SCLCRL, TNUSH, LCTNUCR, ADTRL, TSRL). Furthermore, detailed process, voltage, temperature (PVT), and Monte Carlo simulations verify the robustness of the proposed DOCTRL latch.

A highly reliable and low-overhead quadruple-node-upset tolerant latch design

With the advancement of semiconductor technology and the continual reduction in the feature size of transistors within integrated circuits (ICs), ICs are becoming more and more vulnerable to soft errors induced by energetic particles in harsh radiation environments. To mitigate the impact of soft error on ICs. This paper proposes a quadruple-node-upset tolerant latch (LCQNUT), which consists of two parts: a storage module and a three-stage interception module. The storage module is composed of 12 dual-input inverters. The three-stage interception module is composed of 6 dual-input C-elements (CEs). Based on the CEs and dual-input inverters' blocking capability, the proposed LCQNUT latch can efficiently tolerate the simultaneous upset of any four internal node combinations. Simulation results indicate the proposed LCQNUT latch has the smallest power consumption, area overhead, and area-power-delay product (APDP) compared to the latches with the same soft tolerance ability (D-LATCH, HS-QNU, QNUTL). It has moderate sensitivity to process, voltage, and temperature (PVT).

An ultra low‐power double‐node‐upsets hardened latch design

AbstractIn this paper, a novel low‐cost, double‐node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low‐cost profile. The proposed latch is based on a low‐cost single event double‐node upset tolerant latch and also provides self‐recoverability against double‐node‐upsets. The latch uses clock‐controlled DICE (Dual‐interlocked storage cell) cell and CE(C‐Elements) cell to tolerate double‐node‐upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area‐power‐delay product (APDP) of the proposed low‐power double‐node‐upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature.

Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis.

In recent years, non-volatile memory elements have become highly appealing for memory applications to implement a new class of storage memory that could replace flash memories in sequential logic applications, with features such as compactness, low power, fast processing speed, high endurance, and retention. The memristor is one such non-volatile element that fits the fundamental blocks of sequential logic circuits, the latch and flip-flop; hence, in this article, a non-volatile latch architecture using memristor ratioed logic (MRL) inverter and CMOS components is focused, with an additional memristor as a memory element. A Verilog-A model was used to create the memristor element. The simulation findings validated the compact, low-voltage, and reliable design of the latch design. We evolved in technology enough to create a master-slave flip-flop and arrange it to function as a counter and a shift register. Power, number of elements, cell size, energy, programming time, and robustness are compared to comparable non-volatile topologies. The proposed non-volatile latch proves non-volatility and can store data with a 24% reduction in power consumption and a near 10% reduction in area.

A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

STTSRL: Design of Triple-Node Upset Self-Recovery Latch Based on Schmidt Trigger

With the continuous progress of semiconductor technology, the size of transistors has reduced, and the sensitivity of logic circuits to soft errors caused by radiation has enhanced. The multiple-node upset caused by radiation has affected the reliability of the circuit. This paper proposes a triple-node upset (TNU) self-recovery latch based on the Schmidt trigger (ST) for radiation hardness. The feedback loop is formed by connecting C-elements (CEs) and STs. Using the error filtering mechanism of CE and the hysteresis effect of ST is to realize the reliability of STTSRL. Under the 22 nm PTM process in HSPICE simulation, the STTSRL latch has TNU self-recoverability. Compared with the average value of the same recoverability latch proposed previously, the power consumption, delay, area, number of transistors, and PDAP are reduced by 44.85%, 53.32%, 40.34%, 19.24%, and 83.54%, respectively.

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix

Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments

Due to the gradual reduction of technology size, advanced circuits are more and more impacted by radiation particles. To mitigate multiple-node-upsets (MNUs) of a latch in a harsh radiation environment, and reduce the overhead in power, delay, area, PDP of existing hardened latches, this paper proposed two latches named DTE and 2DTE, respectively. The DTE latch has double-node-upsets (DNUs) tolerability. The 2DTE is constructed by two DTEs and one C-element (CE), which has the capability of tolerating triple-node-upsets (TNUs). Simulation results show that the DTE, compared with existing DNU-tolerance hardened latches, reduces the power, delay, area, and PDP by 53.49 %, 13.1 %, 46.43 % and 59.99 % on average. The 2DTE, compared with existing TNU-tolerance hardened latches, reduces the power, delay, area, and PDP by 52.84 %, 43.2 %, 37.21 %, and 72.04 % on average. The PVT variations are simulated to clearly show that the power consumption of proposed latches is insensitive. The delay sensitivity of DTE is slightly higher than other DNU-tolerant latches, and 2DTE's delay sensitivity is moderate in TNU-tolerant latches.

Low-Complexity Double-Node-Upset Resilient Latch Design Using Novel Stacked Cross-Coupled Elements

With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interlocked storage cell (DICE) element, which exhibit severe limitations: charge sharing during the read operation at a system level and large power consumption. Overcoming these limitations, this brief proposes a DNU-resilient latch based on a novel latch element. The proposed latch fully exploits upset polarity awareness, achieving the maximum number of single-event upset (SEU)-insensitive nodes. We develop a novel double modular redundancy architecture for the DNU-resilient latch design with one SEU-immune module. Based on simulation results, the proposed latch achieves up to 27.6X average power-delay-area-product (PDAP) improvement over state-of-the-art DNU-resilient latches.

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple and quadruple node-upsets. Currently, verifications for error-recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this paper, a latch design protected against MNUs in harsh radiation as well as an algorithm-based verification process are proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

Study on fatigue life of gun latch based on orthogonal test method

Aiming at the problem of fatigue damage of gun latch caused by long-term impact load, the fatigue life of gun latch was studied. Firstly, the finite element model of gun latch was established by using finite element method. Secondly, the static strength and fatigue life of the gun latch were calculated based on S-N curve and Miner’s linear damage accumulation theory. On this basis, the structural factors affecting the fatigue life of the bolt were analyzed, and four factors including the radial diameter of the latch, the axial bearing thickness of the latch, the spiral Angle of the latch support surface and the gun tail support surface, and the locking clearance between the bolt and the gun tail were set up, as well as three variation levels of each factor. Then, the fatigue life of nine groups of gun latches was simulated by orthogonal test method. In addition, the range analysis method was used to analyze the simulation results, and then the influence law and degree of each factor on the fatigue life of gun latch were obtained. Moreover, the optimal combination scheme of the structure parameters of the gun latch was determined by the comprehensive balance method, and then the finite element simulation was carried out to verify the structure of the gun latch. The results show that the maximum stress of the bolt decreases 21.5% and the maximum stress of the gun tail decreases 28.2%, and the maximum stress of the gun bolt is lower than the yield limit of the material. At the same time, the research also shows that the minimum fatigue life of the bolt increases greatly, the minimum fatigue life of the bolt body is 20.8 times of that before the test, and the minimum fatigue life of the gun tail is 102.1 times of that before the test. The results provide a reference for fatigue life analysis and structural design of gun latch.

A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements

As the semiconductor process development, it is shrinking rapidly for the distance of adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to multiple-node-upset (MNU). To effectively mitigate MNU while keeping lower power consumption and delay, this paper proposed a latch design (namely CS-TNURL). The latch consists of four C-elements (CEs), four Schmitt-triggers (STs), seven transmission gates (TGs), and is capable of triple-node-upset (TNU) self-recovery. Besides, this latch uses fewer transistors and clock gating technique, which results in lower power consumption and D-Q delay. Compared with existing latches with TNU self-recoverability, the simulation has shown the proposed latch reduces power consumption by 70 %, delay by 10.62 %, area overhead by 29.71 %, and the power-delay-product (PDP) by 70.34 % on average, respectively. Additionally, the estimation of process, voltage, and temperature (PVT) variation indicated CS-TNURL has a moderate sensitivity towards the PVT variation.

Adapting small jumping robots to compliant environments.

Jumping animals launch themselves from surfaces that vary widely in compliance from grasses and shrubs to tree branches. However, studies of robotic jumpers have been largely limited to those jumping from rigid substrates. In this paper, we leverage recent work describing how latches in jumping systems can mediate the transition from stored potential energy to kinetic energy. By including a description of the latch in our system model of both the jumper and compliant substrate, we can describe conditions in which a jumper can either lose energy to the substrate or recover energy from the substrate resulting in an improved jump performance. Using our mathematical model, we illustrate how the latch plays a role in the ability of a system to adapt its jump performance to a wide range of substrates that vary in their compliance. Our modelling results are validated using a 4 g jumper with a range of latch designs jumping from substrates with varying mass and compliance. Finally, we demonstrate the jumper recovering energy from a tree branch during take-off, extending these mechanistic findings to robots interacting with a more natural environment.

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

This paper presents a novel double node upset (DNU) self-recoverable and single event transient (SET) pulse filterable latch design in 28 nm CMOS technology. The loop structure formed by C-elements (CEs) ensures that the latch can self-recover from the DNUs. A Schmitt trigger at the output can filter out transient pulses from anywhere in the circuit. A clock-controlled inverter channel that connects the input to the output reduces the transmission latency. The simulation results show that the proposed design is completely immune to DNUs, and the delay power area product (DPAP) is reduced by more than 50% compared with the previous design.

Four-input-C-element-based multiple-node-upset-self-recoverable latch designs

As microelectronics technology has continued to progress, the multiple-node upset (MNU), caused by the single-particle and charge-sharing effects, has gradually become one of the most important factors affecting chip reliability. To enhance the reliability of these latches, a TNU completely self-recoverable (TNUCR) latch is first proposed in this paper, mainly consisting of five interlocked four-input C-elements (CEs) and inverters, which are cross-connected to form a ring. For any individual CE, due to the presence of a feedback loop, the value of its output is inverted and becomes the input to the other four CEs, which enables the latch to self-recover from all TNUs. Second, we propose an improved low-cost TNU completely self-recoverable (LCTNUCR) latch. This latch replaces the inverter with a four-input CE and uses a high-speed transmission path (HSTP), which can more rapidly self-recover from all TNU situations. It is demonstrated by experimental results that the two proposed latches are not only TNU tolerant but also TNU self-recoverable. Moreover, based on special design and the adoption of clock gating techniques, the proposed TNUCR latch has a delay-power-area product reduction of about 41.05%, while the proposed LCTNUCR latch has a DPAP reduction of about 71.30% compared to the latest representative TNU hardened latch.

A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.