Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments

Abstract

Due to the gradual reduction of technology size, advanced circuits are more and more impacted by radiation particles. To mitigate multiple-node-upsets (MNUs) of a latch in a harsh radiation environment, and reduce the overhead in power, delay, area, PDP of existing hardened latches, this paper proposed two latches named DTE and 2DTE, respectively. The DTE latch has double-node-upsets (DNUs) tolerability. The 2DTE is constructed by two DTEs and one C-element (CE), which has the capability of tolerating triple-node-upsets (TNUs). Simulation results show that the DTE, compared with existing DNU-tolerance hardened latches, reduces the power, delay, area, and PDP by 53.49 %, 13.1 %, 46.43 % and 59.99 % on average. The 2DTE, compared with existing TNU-tolerance hardened latches, reduces the power, delay, area, and PDP by 52.84 %, 43.2 %, 37.21 %, and 72.04 % on average. The PVT variations are simulated to clearly show that the power consumption of proposed latches is insensitive. The delay sensitivity of DTE is slightly higher than other DNU-tolerant latches, and 2DTE's delay sensitivity is moderate in TNU-tolerant latches.