Abstract

With the advancement of semiconductor technology and the continual reduction in the feature size of transistors within integrated circuits (ICs), ICs are becoming more and more vulnerable to soft errors induced by energetic particles in harsh radiation environments. To mitigate the impact of soft error on ICs. This paper proposes a quadruple-node-upset tolerant latch (LCQNUT), which consists of two parts: a storage module and a three-stage interception module. The storage module is composed of 12 dual-input inverters. The three-stage interception module is composed of 6 dual-input C-elements (CEs). Based on the CEs and dual-input inverters' blocking capability, the proposed LCQNUT latch can efficiently tolerate the simultaneous upset of any four internal node combinations. Simulation results indicate the proposed LCQNUT latch has the smallest power consumption, area overhead, and area-power-delay product (APDP) compared to the latches with the same soft tolerance ability (D-LATCH, HS-QNU, QNUTL). It has moderate sensitivity to process, voltage, and temperature (PVT).

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.