A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements

Abstract

As the semiconductor process development, it is shrinking rapidly for the distance of adjacent transistors in integrated circuits (ICs). Hence, latches are increasingly vulnerable to multiple-node-upset (MNU). To effectively mitigate MNU while keeping lower power consumption and delay, this paper proposed a latch design (namely CS-TNURL). The latch consists of four C-elements (CEs), four Schmitt-triggers (STs), seven transmission gates (TGs), and is capable of triple-node-upset (TNU) self-recovery. Besides, this latch uses fewer transistors and clock gating technique, which results in lower power consumption and D-Q delay. Compared with existing latches with TNU self-recoverability, the simulation has shown the proposed latch reduces power consumption by 70 %, delay by 10.62 %, area overhead by 29.71 %, and the power-delay-product (PDP) by 70.34 % on average, respectively. Additionally, the estimation of process, voltage, and temperature (PVT) variation indicated CS-TNURL has a moderate sensitivity towards the PVT variation.