Large-signal Transistor Research Articles

A Combined Broadband Model for GaN HEMTs in Admittance Domain Based on Canonical Piecewise Linear Functions

In this article, a new large-signal transistor model is proposed. The model combines the advantage of both compact modeling and behavioral modeling techniques, resulting in a new modeling methodology. The intrinsic part of the model is based on the black-box poly-harmonic distortion (PHD) framework, which is implemented using the canonical piecewise linear (CPL) functions. Thus, the new intrinsic model can cover a broad operating frequency band, across a wide range of input powers, using a compact set of model parameters. While at each fixed operating frequency and input power, the model can also accurately predict device behavior over the complete Smith chart. For the extrinsic model, the traditional extrinsic parasitic network is used, enabling access to the intrinsic device plane, as required for waveform engineering. This work examines intrinsic admittance domain models implemented using both the linear and quadratic poly-harmonic expansions. An <inline-formula> <tex-math notation="LaTeX">$8 \times 125\,\,\mu \text{m}$ </tex-math></inline-formula> GaN HEMT device with a 0.25-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gate feature size and a commercial 10-W GaN HEMT is used during the simulation and experimental model validation. Model implementations show excellent interpolation and extrapolation capability over the frequency band across a range of input power levels in both the frequency domain and the time domain.

Ku-Band 50 W GaN HEMT Power Amplifier Using Asymmetric Power Combining of Transistor Cells.

In this paper, we present a Ku-band 50 W internally-matched power amplifier that asymmetrically combines the power transistor cells of the GaN high electron mobility transistor (HEMT) (CGHV1J070D) from Wolfspeed. The amplifier is designed using a large-signal transistor cell model in the foundry process, and asymmetric power combining, which consists of a slit pattern, oblique wire bonding and an asymmetric T-junction, is applied to obtain the amplitude/phase balance of the combined signals at the transistor cell combining position. Input and output matching circuits are implemented using a thin film process on a titanate substrate and an alumina substrate with the relative dielectric constants of 40 and 9.8, respectively. The pulsed measurement of a 330 μs pulse period and 6% duty cycle shows the maximum saturated output power of 57 to 66 W, drain efficiency of 40.3 to 46.7%, and power gain of 5.3 to 6.0 dB at power saturation from 16.2 to 16.8 GHz.

Transistor Model Building for a Microwave Power Heterojunction Bipolar Transistor

This article describes the detailed development of a large-signal transistor model for a microwave power heterojunction bipolar transistor (HBT). Based on the neurospace-mapping (Neuro-SM) technique, this model uses neural networks to map a coarse model space represented by the existing model simulations onto the fine model space represented by device measurements. This article tied for first place in the Microwave Transistor Modeling Student Design Competition at the 2014 IEEE International Microwave Symposium (IMS2014) held in Tampa, Florida.

Extraction of a Model for a Microwave Power pHEMT

This article presents the development of a large-signal transistor model for a power microwave pseudomorphic high-electron mobility transistor (pHEMT). This model won the first prize in the Microwave Transistor Modeling student competition held during the 2013 IEEE Microwave Theory and Techniques Society (MTT-S) International Microwave Symposium (IMS2013) in Seattle, Washington.

A 1–3-GHz Digitally Controlled Dual-RF Input Power-Amplifier Design Based on a Doherty-Outphasing Continuum Analysis

<?Pub Dtl=""?> This paper presents a linear multi-harmonic analysis method to evaluate the performance of digitally controlled dual RF-input power amplifiers (PAs). The method enables, due to its low computational cost, optimization of PA efficiency and bandwidth in a complex design space involving two independent inputs. Under the idealized assumption of short-circuited higher harmonics, the analysis is used to prove the existence of a Doherty-outphasing continuum, featuring high average efficiency over 100% fractional bandwidth. With this result as a foundation, a combiner incorporating microwave transistor parasitics is analyzed without assuming short-circuited higher harmonics, showing that high average efficiencies are also achievable under more realistic conditions. A PA is straightforwardly designed from these calculation results using two 15-W GaN HEMTs. The simulated layout-ready (large-signal transistor model) PA average drain efficiency exceeds 50% over 1.1–3.7 GHz for a 6.7-dB peak-to-average power-ratio WCDMA signal. The measured PA has a maximum output power of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{44}} \pm {\hbox{0.9}}$</tex></formula> dBm and a 6-dB output power back-off (OPBO) power-added efficiency (PAE) of 45% over 1–3 GHz. After applying digital pre-distortion, excellent linearity is demonstrated when transmitting the WCDMA signal, resulting in an adjacent channel leakage power ratio lower than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{\hbox{57}}$</tex></formula> dBc with corresponding average PAE of 50% and 40% at 1.2 and 2.3 GHz, respectively. This is, to the authors' knowledge, the most wideband OPBO efficiency enhanced PA reported to date, proving the effectiveness of employing linear multi-harmonic analysis in dual-input PA design.

Design and model studies for solid-state power amplification at 210 GHz

The high millimeter-wave (mmW) frequency range offers new possibilities for high-resolution imaging and sensing as well as for high data rate wireless communication systems. The use of power amplifiers of such systems boosts the performance in terms of operating range and/or data rate. To date, however, the design of solid-state power amplifiers at frequencies about 210 GHz suffers from limited transistor model accuracy, resulting in significant deviation of simulation and measurement. This causes cost and time consuming re-design iterations, and it obstructs the possibility of design optimization ultimately leading to moderate results. For verification of the small-signal behavior of our in-house large-signal transistor model, S-parameter measurements were taken from DC to 220 GHz on pre-matched transistors. The large-signal behavior of the transistor models was verified by power measurements at 210 GHz. After model modification, based on process control monitor (PCM) measurement data, the large-signal model was found to match the measurements well. A transistor model was designed containing the statistical information of the PCM data. This allows for non-linear spread analysis and reliable load-pull simulations for obtaining the highest available circuit performance. An experimental determination of the most suitable transistor geometry (i.e. number of gate fingers and gate width) and transistor bias was taken on 100 nm gate length metamorphic high electron mobility transistor (mHEMT) transistors. The most suitable combination of number of fingers, gate width and bias for obtaining maximum gain, maximum output power, and maximum power added efficiency (PAE) at a given frequency was determined.

New Time-Domain Voltage and Current Waveform Measurement Setup for Power Amplifier Characterization and Optimization

This paper reports a novel voltage and current waveform measurement system suitable for large-signal transistor and power amplifier characterization and optimization. This technique is original in its use of a double six-port (SP) reflectometer as a homodyne vector network analyzer, which is calibrated in magnitude and phase by means of a reference multiharmonic signal generator, to measure the waveforms at the output terminal of the device. An active branch load-pull setup is used to control the source impedance at the fundamental frequency, and the load impedance at the fundamental, second, and third harmonic frequencies. The capability of the proposed SP reflectometer-based configuration is demonstrated experimentally, by measuring the voltage and current waveforms of a GaAs metal-semiconductor field-effect transistor that is biased in class AB and tuned for maximum efficiency. To assess the level of accuracy of the proposed method, the same waveforms were also measured using a microwave-transition-analyzer-based system. A comparison of the results shows that the proposed SP reflectometer setup obtains results accurate enough for power amplifier characterization with lower equipment cost.

A Systematic State-Space Approach to Large-Signal Transistor Modeling

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A state–space approach to large-signal (LS) modeling of high-speed transistors is presented and used as a general framework for various model descriptions of the dispersive features frequently observed for HEMTs at low frequency. Ensuring unrestricted LS–small-signal (SS) model compatibility, the approach allows to construct LS models from multibias SS <formula><tex>$S$</tex> </formula>-parameter measurements. A general transformation between state–space models is derived, which are equivalent in the SS limit, but nonequivalent under LS stimuli. This transformation has the potential to compensate deviations observed by comparing model predictions with LS measurements and to find an optimum state linear LS model without any change of the SS behavior. </para>

Characterization and modeling of AlGaN/GaN MOS capacitor with leakage for large signal transistor modeling

Dual mode AlGaN/GaN metal oxide semiconductor (MOS) heterostructure field-effect transistor (HFET) devices were fabricated and characterized. In HFET mode of operation the devices showed an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /spl middot/L/sub g/ product of 12GHz/spl middot/μm at Vgs=-2 V. The AlGaN devices showed formation of an accumulation layer under the gate in forward bias and a f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /spl middot/L/sub g/ product of 6GHz/spl middot/μm was measured at Vgs=5 V. A novel piecewise small signal model for the gate capacitance of MOS HFET devices is presented and procedures to extract the capacitance in presence of gate leakage are outlined. The model accurately fits measured data from 45MHz to 10GHz over the entire bias range of operation of the device.

Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model

The improved RF performance of silicon-based technologies over the years and their potential use in telecommunication applications has increased the research in RF modelling of MOS transistors. Especially for analog circuits, accurate RF small signal and large signal transistor models are required. In this paper, we propose an accurate, non-quasi-static, large signal (i.e., nonlinear) RF MOSFET model. Our model consists of a current source and a charge source at the drain terminal and a charge source at the gate terminal. The sources' magnitudes are calculated from the gate-bias and drain-bias dependent elements of the MOSFET equivalent circuit. The MOSFET equivalent circuit elements on itself are extracted from S-parameters at all gate voltages and drain voltages that occur in large signal operation. The accuracy of the equivalent circuit based model is validated by large signal RF measurements using a nonlinear network measurement system. Large signal modelling results using the BSIM3v3 compact model are also presented. Both the equivalent circuit based model and the BSIM3v3 model meet the requirements to describe accurately the RF large signal behaviour of MOS transistors.

New measurement-based technique for RF LDMOS nonlinear modeling

In this letter a new look-up table model is developed for the nonlinear modeling of radio frequency (RF) LDMOS transistors. The modeling technique is based on the use of approximation splines that are coupled to a pulsed I-V characterization setup. It provides a very fast modeling procedure, while avoiding the appearance of undesired ripples in the modeled functions. The technique has been applied to a RF LDMOS technology for L-band applications, obtaining excellent results in the prediction of both the small- and large-signal transistor responses. This technique is specially suitable for fast-evolution technologies.

An improved calibration technique for on-wafer large-signal transistor characterization

The on-wafer measurement of complex quantities and absolute power levels of active devices is truly significant for nonlinear device characterization and modeling. An original procedure, which allows one to perform both the vector and the power calibrations at the RF wafer probe tips used for on-wafer measurement of two-port devices, is presented. The measurement system is based on an automatic vector network analyzer with coaxial directional couplers and RF coplanar wafer probes. A new error model of the dual directional coupler, which samples the power waves traveling at device output, allows one to take advantage of the coaxial section at the output of the measuring system for calibrating the power level up to the on-wafer probe tips. >

A charge-based large-signal bipolar transistor model for device and circuit simulation

A model derived from one-dimensional regional analyses of ambipolar carrier transport with minimal empiricism is presented. Model verification and parameter extraction, based on test devices representative of the advanced bipolar technology, are described and used to demonstrate the predictive potential of the model. The physical model serves as a basis for seminumerical mixed-mode device/circuit simulation, as well as for a model hierarchy, in CAD applications. >

An investigation of the power characteristics and saturation mechanisms in HEMTs and MESFETs

A method for large-signal transistor analysis is presented. The method is based on the harmonic-balance approach but makes use of input data from measured S-parameters instead of DC or pulsed DC characteristics and a large-signal equivalent circuit with harmonic elements. The topology of this circuit is nearly identical to commonly used small-signal equivalent circuits; its application allows a detailed interpretation of the computed results, which are very precise due to the use of small-signal S-parameters. The large-signal model is applied to HEMTs and MESFETs. Their saturation mechanisms are investigated and the operational difference is discussed. The importance of including higher harmonic signal components in the large-signal analysis is also shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A compact physical large-signal model for high-speed bipolar transistors at high current densities&amp;#8212;Part I: One-dimensional model

A compact physical large-signal transistor model is presented that is suited for simulating high-speed bipolar IC's even if the transistors are operated deeply within the high-current region (including quasi-saturation). Like the well-known and currently used Gummel-Poon model, it is based on the integral charge-control relation (ICCR) proposed by Gummel. However, in the high-current region it shows much better accuracy, especially for high-frequency and switching operation. This is mainly a result of the fact that the transit time (and thus the minority-carrier charge) is chosen as a basic model parameter, which is carefully measured and accurately approximated by analytical expressions throughout the total interesting operating range. In Part I of the work, presented here, the model and its parameters are described for the one-dimensional case. Its validity is verified by comparison with exact numerical transistor simulations of both the dc characteristics and the switching behavior. The simulations are based on doping profiles that are typical of transistors in high-speed IC's. Methods for determination of the model parameters are presented. In Part II [1], the model is extended to the two-dimensional case, i.e., to real transistors. It is experimentally verified by measuring the dc characteristics and the switching behavior of very fast transistors with high transit frequency (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> ≈ 7 GHz) and small emitter stripe width. The complete model, which is called HICUM (from "high-current model"), was already implemented in the circuit analysis program SPICE 2.

Modeling of High-Speed, Large-Signal Transistor Switching Transients from s-Parameter Measurements

A new technique has been developed to derive the large-signal transient response of semiconductor devices from small-signal frequency response data. The large-signal switching response can be calculated for an arbitrary input signal voltage and rise time. The new technique utilizes the Fourier transformation to combine arrays of small-signal data to compute the response waveform. The input waveform is decomposed into a superposition of small pulses. The response to each pulse is obtained by Fourier transformation techniques, using s-parameter data at appropriate bias points. The sum of these responses approximates the overall transient response. Simulations were performed for a GaAs MESFET for step inputs with the rise times of 8 ns and 150 ps. Good agreement was obtained between simulated waveforms and measured output waveforms in rise time, magnitude, and waveform shape. This algorithm is general and will work for other measured small-signal transfer parameters as functions of frequency and bias.

Modeling of high-speed, large-signal transistor switching transients from s-parameter measurements

A new technique has been developed to derive the large-signal transient response of semiconductor devices from small-signal frequency response data. The large-signal switching response can be calculated for an arbitrary input signal voltage and rise time. This new technique utilizes the Fourier transformation to combine arrays of small-signal data to compute the response waveform. The input waveform is decomposed into a superposition of small pulses. The response to each pulse is obtained by Fourier transformation techniques, using s-parameter data at appropriate bias points. The sum of these responses approximates the overall transient response. Simulations were performed for a GaAs MESFET for step inputs with the rise times of 8 ns and 150 ps. Good agreement was obtained between simulated waveforms and measured output waveforms in rise time, magnitude, and waveform shape. This algorithm is general and will work for other measured small-signal transfer parameters as functions of frequency and bias.

A Modified Ebers-Moll Transistor Model for RF-Interference Analysis

This paper develops analytical techniques for the study of nonlinear RF and microwave effects in semiconductor devices. Rectification in p-n junctions is discussed, and a novel large-signal transistor model is developed, based upon modifications to standard Ebers-Moll formulations for bipolar transistors. Use of the models in worst-case analysis is discussed, with ranges of parameters given based on a simplified analysis of rectification in ideal diodes.

Design technique for broadband microwave transistor power amplifiers

A technique for the design of broadband microwave transistor power amplifiers is presented that utilises the powerful methods of network synthesis to achieve optimum large-signal performance. Only two large-signal transistor measurements per frequency are required to achieve a good analytic model of the transistor's variation of added power with load impedance, and a mapping function is presented that translates this added-power characteristic into an equivalent linear-circuit reflection-coefficient characteristic. With this representation, methods of linear-network synthesis are used to obtain circuits which optimise the amplifier's added-power efficiency over a broad range of frequencies. The design technique has been experimentally verified by the characterisation, design and construction of a b.j.t. amplifier of near-octave bandwidth centred at 1 GHz, with the large-signal performance in good agreement with that predicted by the design theory.

Erratum: Improving the large-signal models of bipolar transistors by dividing the intrinsic base into two lateral sections

In large-signal transistor models, the lateral voltage drop across the base region is usually represented by a single-lump constant base spreading resistance. The letter demonstrates, for the switching mode, that a much better approximation of the 2-dimensional transistor can already be achieved by dividing the intrinsic base into merely two sections (2-section model).