Large Combinational Circuits Research Articles

Temperature effects on BTI and soft errors in modern logic circuits

Since thermal responses of the drive current in recent 3D FinFET and conventional planar transistors are different, addressing performance and reliability in advanced VLSI circuits must be reconsidered. This study investigates temperature effects on two of the most problematic reliability issues in modern logic circuits, namely Bias Temperature Instability (BTI) and soft errors. In particular, we initially examine the inversion of temperature effect that strengthens the drive current in 14-nm bulk tri-gate FinFETs with increasing temperature, and model it as a source of threshold voltage reduction. This temperature-induced threshold voltage variation is consequently adapted into our proposed simulation and analysis framework for BTI degradation in large combinational circuits. The BTI aging results from our proposed estimation are more pessimistic than that from the conventional approach where the temperature effect is excluded. Simulation results show that long-term BTI aging delay worsens as temperature increases, yet the domination of thermal effect on the drive current leads to overall performance improvement in all circuits under 10-year BTI stress. In addition, soft errors and their masking probabilities in logic circuits are addressed under the inversion of temperature effect and supply voltage variation. The results reveal that soft error immunity in all experimental circuits improves significantly with increasing supply voltage and temperature, mainly due to the increase of critical charge. The average relative soft error rate when the supply voltage changes from 0.4 V to 0.6 V and 0.8 V at 0 °C is as low as 3.7% and 0.08% of the average result at 0.4 V, respectively. On average, the relative soft error rate at a particular supply voltage when temperature changes from 0 °C to 40 °C, 80 °C, and 120 °C is around 70%, 50%, and 30% of the average result at 0 °C, respectively.

A Scalable Solution to Soft Error Tolerant Circuit Design Using Partitioning-Based Gate Sizing

Current technology scaling trends aggressively increases the susceptibility of combinational circuit reliability to radiation-induced transient faults (which also known as soft errors). Various gate sizing techniques have been used to reduce soft error rate (SER) in the past, but their main drawback is that they are expensive in term of run time. These methods require changes to adapt to the large scale circuits. In this paper, an efficient circuit partitioning-based gate sizing method is presented, which significantly speeds up the gate sizing optimization process. In the proposed method, the circuit is divided into the topologically levelized small subcircuits by cone structures. Then, the subcircuits which are located in the same level are resized individually and independently. The subcircuit error probability (SEP) metric is introduced to evaluate the contribution of each subcircuit into the total circuit SER. The key idea of the proposed method is to evaluate the effects of each gate sizing on circuit reliability locally using SEP instead of global evaluation by the total circuit SER. Such evaluation results in speeding up the gate sizing optimization process. Experimental results show that the proposed approach is about 280× orders of magnitude faster than the sensitivity-based gate sizing approach [R. R. Rao, D. Blaauw, and D. Sylvester, “Soft error reduction in combinational logic using gate resizing and flipflop selection,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des. , 2006, pp. 502–509] while it can achieve up to 45% reduction in circuit SER with less than 17% area overhead. This level of speed and efficiency makes the proposed approach a viable solution to mitigate the SER of very large combinational circuits used in industry.

Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields

This paper introduces a technique to derive a word-level abstraction of the function implemented by a combinational logic circuit. The abstraction provides a canonical representation of the function as a polynomial ${Z} {= {\mathcal {F}}(A)}$ over the finite field $ {{\mathbb {F}}_{2^{k}}}$ , where ${Z}$ and $ {A}$ represent the ${k}$ -bit output and input bit-vectors (words) of the circuit, respectively. This canonical abstraction can be utilized for formal verification and equivalence checking of combinational circuits. Our approach to abstraction is based upon concepts from computational commutative algebra and algebraic geometry. We show that the abstraction ${Z} {= {\mathcal {F}}(A)}$ can be derived by computing a Grobner basis of the polynomials corresponding to the circuit, using a specific elimination term order derived from the circuit’s topology. Computing Grobner bases using elimination term orders is infeasible for large circuits. To overcome this limitation, we describe an efficient symbolic computation to derive the word-level polynomial. Our algorithms exploit: 1) the structure of the circuit; 2) the properties of Grobner bases; 3) characteristics of finite fields $ {{\mathbb {F}}_{2^{k}}}$ ; and 4) modern algorithms from symbolic algebra, to derive the canonical polynomial representation. This approach is employed to verify (and detect bugs in) large combinational finite field arithmetic circuits, where contemporary verification techniques are known to be infeasible.

A Novel Layout-Based Single Event Transient Injection Approach to Evaluate the Soft Error Rate of Large Combinational Circuits in Complimentary Metal-Oxide-Semiconductor Bulk Technology

As the technology scales down, space radiation induced soft errors are becoming a critical issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout-based Single-Event Transient (SET) injection approach to evaluate the Soft Error Rate (SER) of large combinational circuits in Complementary Metal-Oxide-Semiconductor (CMOS) bulk technology. We consider the effect of ion strike location on the SET pulse width in this approach. Heavy-ion experiments on two different inverter chains are conducted to verify this layout-based SET injection approach. The simulation and experiment results show that this approach can fairly reflect the SET pulse width distribution. Furthermore, we compare the soft error number calculated by our proposed layout-based approach with the normal SET injection approach, and illustrate the detailed circuit response obtained by our proposed approach.

Optimised reversible divider circuit

Reversible logic has received a great deal of attention from many researchers over recent years for its enormous potential for application in quantum computing and nanotechnology due to its ability to reduce power consumption, which is the main requirement in low power VLSI design. In this study, first, we have presented new reversible blocks. These circuits can be used for the design of a large and complex combinational circuit. Then, we presented optimised designs for the various reversible components: multiplexers, registers, and shift registers. We will put forward the design and evaluation of optimised reversible division hardware to submit an application of reversible logic design. The comparative results show that the proposed designs individually have less hardware complexity, garbage outputs, constant inputs, quantum cost and significantly better scalability than the existing works. We have presented some lower bounds on the cost-metrics for designing the reversible components of the divider circuit.

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

A novel constrained layout placement approach is proposed to enhance the pulse quenching effect in combinational circuits. This constrained algorithm can enlarge the number of quenching cells and shrink the distance between these cells. Simulation results illustrate that the soft error vulnerabilities are effectively reduced by adopting this novel constrained layout placement algorithm with no area penalty.

Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology

Mitigating the SERs of large combinational circuits by using half guard band technique in CMOS bulk technology

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.

EFFICIENTLY MAPPING LARGE COMBINATIONAL CIRCUITS ON K-LUT BASED FPGAS

Large combinational circuits need to be partitioned in order to manage scarce resources on k-LUT based FPGAs. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented a multilevel multi-resource partitioning algorithm for partitioning large combinational circuits using cone-clusters in order to efficiently map existing and commercially available k-LUT based FPGAs packages.

Comparison of SEUTool results to experimental results in boeing radiation tolerant DSP (BDSP C30)

A CAD tool (SEUTool) is analyzed for simulating single-event upsets (SEUs) in large combinational logic circuits. SEUTool cross-section results show excellent agreement with experimental test data taken with the Boeing BDSP C30.

A fast and accurate delay dependent method for switching estimation of large combinational circuits

Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented.

Functional complexity estimation for large combinational circuits

A disjoint cube-based method for fast computation of Karpovsky's functional complexity measure is presented. A modification to the method for generating a disjoint sum of cube representations for a combinational system is also presented, which results in improved speed performance in the generation of disjoint sum of cubes. The proposed algorithms are tested on several benchmark circuits. The results obtained demonstrate the efficiency of the proposed algorithms.

Bridge fault diagnosis using stuck-at fault simulation

A new diagnostic fault simulator is described that diagnoses both feedback and nonfeedback bridge faults in combinational circuits while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals problem. Sets representing nodes possibly involved in a defect are partitioned based on logic and fault simulation of failing vectors. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits containing Boolean primitives and has achieved over 98% accuracy for nonfeedback bridge faults and over 85% accuracy for feedback bridge faults with good diagnostic resolution.

Design-for-testability for path delay faults in large combinational circuits using test points

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testable circuit. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. When the number of paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform test-point insertion directly targeting the path delay faults that are still untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Predicting the complexity of large combinational circuits through symbolic spectral analysis of their functional specifications

The use of symbolic data structures to store pseudo-Boolean (i.e. integer-valued) functions has proved to be extremely effective in handling both transform matrices and spectral representations of large Boolean functions. The authors propose a novel application of symbolic spectral analysis techniques to the prediction of the complexity of a combinational circuit. They present a symbolic formulation of the problem, and propose an implicit algorithm for its solution that performs well, in terms of both execution time and accuracy in the computation, on circuits that are sensibly larger than the ones usually handled by the tools currently available. Experimental results, collected on standard examples, are discussed to support this claim.

D-CPT: a time/space efficient fault simulator

Abstract A new fault simulation method, deductive critical path tracing (D-CPT), for very large combinational circuits is proposed. The simulator uses both the deductive fault propagation technique (used in deductive fault simulation (DFS)) and the critical path tracing (CPT) method in forming the D-CPT. Deductive fault propagation is not performed on the whole fault set of a circuit as in DFS but instead only on a partial fault set, i.e., those faults on fanout stems. The capture lines of each fanout fault are determined, and used to resolve the difficulty in determining the criticality of a fanout stem during the CPT process. Furthermore, the huge storage requirement of DFS is sharply reduced to an acceptable level when handling very large circuits. Experiments on ISCAS benchmark circuits show that the proposed method is both efficient and complete.

An Algorithm to Generate Random Large Combinational Circuits

This paper describes an efficient algorithm for generating large combinational circuits (ca. 10 5 -10 6 gates). The method has been applied to construct networks for testing the performance of new VLSI chip fabrication processes and as a means of producing testbeds for assessing the average performance of digital simulation systems

A partitioning technique for reducing the computational complexity of probabilistic fault detection in general combinational circuits

This paper examines the impacts of different types of circuit partitioning on reducing the computational complexity for computing the fault detection probability, which usually grows exponentially with the number of input lines in the given circuit. Partitioning a large combinational circuit into arbitrary subcircuits does not, in general, reduce the computational time complexity of the fault detection probability. In fact, partitioning a given circuit into general subcircuits is expected to increase the time complexity by the amount of time spent in the partition process itself. Nevertheless, it will be shown that decomposing a general combinational circuit into its modules (supergates) such that these modules constitute the basic elements of a tree circuit (network) considerably reduces the computational complexity of the fault detection probability problem. Toward this goal, two algorithms are developed. The first partitions a given circuit into maximal supergates whenever this is possible. Its computa...

Confidence intervals for expected coverage from a beta testability model

The testability distribution of a VLSI circuit can be used to predict the fault coverage of a set of test patterns by restricting the standard test pattern generation process to a sample of faults. When testability of a VLSI circuit is modeled as a beta distribution, the random detection counts obtained have a beta-binomial distribution. This paper includes: a) three confidence intervals for the parameters of the beta-binomial distribution; b) a determination of the proper sample size needed such that the theoretical confidence intervals agree with the actual ones; and c) a determination of the effect of the number of generated tests on confidence interval widths. Restricting the test generation process to a sample of faults results in major savings in the overall costs of test generation. Experimental results are given on three of the large combinational benchmark circuits (presented at the 1985 International Symposium on Circuits and Systems).

Pseudo-random test generation for large combinational circuits

In this paper, a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing. Several interesting experimental results are obtained. It is found out that initial states of pseudo-random sequences have little effect on fault coverage. Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stagesm is less than the number of circuit inputsn leads to low fault coverage, and the fault coverage is reduced asm decreases. The local unrandomness of pseudo-random sequences is exposed clearly. Generally, when an LFSR is employed as a pseudo-random generator, there are at least as many LFSR stages as circuit inputs. However, for large circuits under test with hundreds of inputs, there are drawbacks of using an LFSF with hundreds of stages. In the paper, a new design for a pseudo-random pattern generator is proposed in whichm<n. The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary fault coverage. It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage, and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.