Pseudo-random test generation for large combinational circuits

Abstract

In this paper, a simulation system of pseudo-random testing is described first to investigate the characteristics of pseudo-random testing. Several interesting experimental results are obtained. It is found out that initial states of pseudo-random sequences have little effect on fault coverage. Fixed connection between LFSR outputs and circuit inputs in which the number of LFSR stagesm is less than the number of circuit inputsn leads to low fault coverage, and the fault coverage is reduced asm decreases. The local unrandomness of pseudo-random sequences is exposed clearly. Generally, when an LFSR is employed as a pseudo-random generator, there are at least as many LFSR stages as circuit inputs. However, for large circuits under test with hundreds of inputs, there are drawbacks of using an LFSF with hundreds of stages. In the paper, a new design for a pseudo-random pattern generator is proposed in whichm<n. The relationship between test length and the number of LFSR stages is discussed in order to obtain necessary fault coverage. It is shown that the design cannot only save LFSR hardware but also reduce test length without loss of fault coverage, and is easy to implement. The experimental results are provided for the 10 Benchmark Circuits to show the effectiveness of the generator.