kV 4H-SiC Research Articles

Design Considerations for Robust Manufacturing and High Yield of 1.2 kV 4H-SiC VDMOS Transistors

Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.

Design Optimization of 1.2kV 4H-SiC Trench MOSFET

In a trench MOSFET structure, p+ trench bottom implant (also called p+ shielding region) is commonly used to protect the gate oxide from high electric field stress, however, if the design and fabrication process are not optimized properly, the p+ shielding region together with n-drift and the p-base region will form a parasitic JFET which severely degrades the on-state performance of the device. This paper presents this parasitic JFET effect with experimental results and the optimization work that has been done to eliminate the parasitic JFET.

Correction of the Reverse Recovery Characteristics of High-Voltage 4H-SiC Junction Diodes Using Proton Irradiation

The effect of proton irradiation on the electrical characteristics of high-voltage (3 kV) 4H-SiC junction diodes is studied. The diodes are irradiated through a 10-μm-thick Ni mask. The proton energy and the irradiation dose are 2.8 MeV and 4 × 1011 cm–2, respectively. After irradiation, the forward differential resistance of the diodes increased by ~35%, the reverse-recovery charge decreased by a factor of ~3, and the nature of the reverse recovery became “hard.”

Design and fabrication of 10-kV silicon–carbide p-channel IGBTs with hexagonal cells and step space modulated junction termination extension**Project supported by the National Basic Research Program of China (Grant No. 2015CB759600), the Science Challenge Project, China (Grant No. TZ2018003), the National Natural Science Foundation of China (Grant Nos. 61474113, 61574140, and 61804149), the Beijing NOVA Program, China (Grant Nos. 2016071 and

10-kV 4H–SiC p-channel insulated gate bipolar transistors (IGBTs) are designed, fabricated, and characterized in this paper. The IGBTs have an active area of 2.25 mm2 with a die size of 3 mm × 3 mm. A step space modulated junction termination extension (SSM-JTE) structure is introduced and fabricated to improve the blocking performance of the IGBTs. The SiC p-channel IGBTs with SSM-JTE termination exhibit a leakage current of only 50 nA at −10 kV. To improve the on-state characteristics of SiC IGBTs, the hexagonal cell (H-cell) structure is designed and compared with the conventional interdigital cell (I-cell) structure. At an on-state current of 50 A/cm2, the voltage drops of I-cell IGBT and H-cell IGBT are 10.1 V and 8.3 V respectively. Meanwhile, on the assumption that the package power density is 300 W/cm2, the maximum permissible current densities of the I-cell IGBT and H-cell IGBT are determined to be 34.2 A/cm2 and 38.9 A/cm2 with forward voltage drops of 8.8 V and 7.8 V, respectively. The differential specific on-resistance of I-cell structure and H-cell structure IGBT are and , respectively. These results demonstrate that H-cell structure silicon carbide IGBT with SSM-JTE is a promising candidate for high power applications.

Коррекция характеристик обратного восстановления высоковольтных инжекционных 4H-SiC диодов с помощью протонного облучения

The effect of proton irradiation on electrical characteristics of high-voltage (3 kV) 4H-SiC junction diodes have been investigated. The diodes were irradiated through 10-µm thick Ni-film. The energy of protons and irradiation dose were 2.8 MeV and 4×1011 cm-2, respectively. After proton irradiation, the diodes exhibited 35-% increasing in on-state resistance, about 3 times decreasing in the reverse recovery charge with the reverse recovery character being "hard".

Updated trade-off relationship between specific on-resistance and breakdown voltage in 4H-SiC{0001} unipolar devices

The minimum specific on-resistance of 4H-SiC{0001} unipolar devices as a function of the breakdown voltage was updated based on latest studies on intrinsic physical properties, such as impact ionization coefficients. Both punch-through (PT) and nonpunch-through (NPT) structures were considered, because a PT structure generally gives a lower on-resistance at a given breakdown voltage. The minimum specific on-resistance of 1 kV 4H-SiC devices can be as low as 0.20 mΩ cm2 at room temperature. An analytical expression for the relationship between the specific on-resistance and breakdown voltage is given.

Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes

An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.

Experimental Demonstration on Ultra High Voltage and High Speed 4H-SiC DSRD with Smaller Numbers of Die Stacks for Pulse Power

This paper presents the experimental results of static and dynamic characteristics of the newly developed 14 kV 4H-SiC high-speed drift step recovery diode (DSRD) for pulse power applications for the first time. The feature of the diode structure is to be designed based upon the p+/p-/n+ structure and is to make an additional extremely low doping and thin n-drift layer between the p-drift layer and n+ substrate. This device successfully exhibits higher breakdown voltage of 14kV and high-speed voltage pulse in a range of a few nanoseconds, simultaneously.

Effect of Design Variations and N<sub>2</sub>O Annealing on 1.7kV 4H-SiC Diodes

In this work we have studied the influence of design and process variations on electrical performance of 1.7 kV 4H-SiC Schottky diodes. Diodes with two variations in their active region design namely, stripe design and segment design, were fabricated in this study. Field Limiting Rings (FLRs) or Junction Termination Extension (JTE) were used as edge termination design to achieve a blocking voltage of 1.7 kV. In addition to these designs an extra processing step of nitrous oxide (N2O) annealing was performed on some of the diodes. The study has shown that there is no extra beneficial effect of nitrous oxide annealing on device characteristics.

1.2 kV 4H-SiC Split-Gate Power MOSFET: Analysis and Experimental Results

This paper presents a 1.2kV-rated 4H-SiC Split-Gate power MOSFET (SG-MOSFET) with superior high frequency figures-of-merit (HF-FOM). Electrical characteristics including reverse transfer capacitance and gate-to-drain charge are measured from fabricated devices on a 6-inch SiC wafer, demonstrating excellent performance. Compared to the conventional MOSFETs, the SG-MOSFET provides about 7x smaller HF-FOM [RonxCgd] and 2x smaller HF-FOM [RonxQgd] with improved reverse transfer capacitance and gate-to-drain charge.

Effects of trench profile and self-aligned ion implantation on electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs using bottom protection p-well

The effects of a trench profile and self-aligned ion implantation on the electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs employing a bottom protection p-well (BPW) were investigated to improve blocking capability by simulation studies. The trench profile and thickness of a SiO2 spacer during self-aligned ion implantation for BPW affect electrons flow through a trench gate as well as E-field concentration at the gate insulator on a trench bottom. At trench angle higher than 84° and a SiO2 spacer thicker than 0.2 µm showed that the Al concentration penetrated into the trench sidewall during ion implantation is less than 0.3% in comparison with the background doping concentration in a drift region. Under the optimum conditions with a trench angle of 90° and 0.2-µm-thick SiO2 spacer, a high breakdown voltage of 1.45 kV with a low E-field peak in the gate insulator was achieved.

The Effect of Threading Dislocation on Current-Voltage Characteristics of 3.3kV 4H-SiC Schottky Barrier Diode

Silicon carbide (SiC) is an attractive semiconductor for high-power, high-temperature, and high-frequency electronic devices due to its wide bandgap, high breakdown electric field, and high thermal conductivity. However, the development and commercialization of SiC-based devices are slow due to SiC defects. SiC growth technology has also been developed so much that killer defects, including micropipes, triangular defects and basal plane dislocation that degrade device performance, have been reduced. Although many researches have reported the degradation of devices performance caused by various crystal defects in SiC, the studies on the effect of threading dislocations (TDs) is still insufficient [1,2]. In this paper, we studied the effect of TDs on current-voltage (I-V) characteristics of 3.3 kV 4H-SiC Schottky barrier diodes (SBDs). The 3.3 kV SBDs were fabricated on a n-type 4H-SiC epitaxial wafer. The thickness of epitaxial layer was 28 um and its doping concentration 1 × 1015 cm-3. The boron (NA: 2.0 × 1018 cm-3) was implanted to form the junction termination extension (JTE) that helps to reduce electric field crowding at Schottky metal edge. The aluminum (ND,max: 5.0 × 1019 cm-3) was implanted to form ohmic contact for robust reverse blocking at the periphery of active region. The ion-implanted samples were annealed at 1700 °C for 60 m in Ar ambient. Nickel (Ni) was firstly depotied to form the front-side ohmic contact and cathod electrode, and annealed at 950 °C. Schottky metal, Ni, is deposited and then wet-etched to define the active regions. Post-annealing was performed at 300 °C. The crystal defects and process defects caused during diode fabrication on the active region were observed using electron beam induced current (EBIC) and X-ray topography (XRT). The I-V measurement were performed for forward and reverse I-V charateristics. To study the effet of dislocation on electrical properties of fabricated SBDs, I-V characteristies were analyzed. The Schottky barrier height (SBH) and ideality factor (IF) were extracted from forward characterisitics. The extracted average SBH and IF of SBDs were 1.5 eV and 1.05, respectively. The average leakage current was about 10-12 A at the reverse bias of -100V. The breakdown voltages increased with the length of JTE. The observed maximum breakdown voltage was 4.6 kV. The defects in acvitve region of all measured devices were analyzed using XRT technique to compare with electrical characteristics. The TDs did not affect the forward I-V charcteristecs. However the process defects degraded the forward characteristics, such that the ideality factor was increased from 1.05 to 1.4. These process defect significantly increased the leakage current to 10-7 A and reduced the breakdown below 1 kV. Therefore, the process defects during fabrication are fatal to the device performance. The leakage current of the devices observed TDs at active region increased compared with devices without defect. The breakdown voltage of fabricated 3.3 kV SBDs was not significantly affected by crystal defects. This meas that the TDs are not fatal defect for SBDs having rating breakdown voltage of 3.3 kV. Nevertherless, the increase in the leakage current of a device having the TDs may cause long-term reliability issues. Therfore, it is necessary to determine allowable type of defects and their defect density for highly reliable SiC power devices. [1] H. J. Jung, S. B. Yun, I. H. Kang, J. H. Moon, W. J. Kim, W. Bahng, Mater. Sci. Forum, 821-823 (2015) 563-566. [2] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, T. Endo, Appl. Phys. Lett., 100 (2012) 242102. Figure 1

Electrical and Material Properties Analysis of 5kV 4H-SiC Schottky Barrier Diodes

Silicon carbide is an attractive material for next-generation power devices, it has wide band gap and high thermal conductivity. SiC power devices can operate at higher temperatures and voltages compared to silicon devices. But, electrical characteristics of the SiC power devices can be deteriorated by SiC defects. The killer defects such as micropipes and stacking faults have been reduced through the development of SiC growth technique. But still the threading dislocations (TDs) and basal plane dislocations (BPDs) lowered the breakdown voltage and increased the leakage current during device operation [1]. In this study, we fabricated the 5 kV 4H-SiC Schottky barrier diode (SBD) to study the effect of SiC defect on electrical properties of SiC SBDs. The thickness of epitaxial layer was 50 um and the doping concentration is 1E15 cm-3. The device was fabricated with various length of junction termination extension (JTE). Ion implantation was performed to form p surge (Al, 500 °C, 5E19 cm-3) and JTE (B, 500 °C, 2E18 cm-3) regions. Activation annealing was performed at 1700 °C for 60 m. 100 and 30-nm-thick Ni were deposited as the cathode and front-side ohmic metal respectively, and then annealed at 950 °C for 90 s in RTA system. Finally, 100-nm-thick Ni was sputtered on front-side as a Schottky contact metal. We investigated the forward, reverse characteristics, and reverse breakdown voltage of the fabricated 4H-SiC SBDs. The diode characteristics, ideality factor (IF) and Schottky barrier height (SBH) were obtained from the forward electrical characteristics, about the 1.23 and 1.3 eV, respectively. The relative highly ideality factor may be due to rough surface of thick epitaxial layer. The breakdown voltage was obtained above 5 kV with JTE length longer than 60 um. During reverse characteristics the electrically weak points were observed using electroluminescence (EL). The EL spot was mainly aroused from electrically leaky points, it mostly observed at the edge of JTE. Some EL spots were observed inside the JTE or active region. The defects of the fabricated 4H-SiC 5 kV SBDs were analyzed using non-destructive analysis method, X-ray topography (XRT) and electron beam induced current (EBIC). We tried to determine the correlation between the electrical characteristics of the device and the crystal defects in the device. [1] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, and T. Endo, Appl. Phys. Lett. 100, 242102 (2012). Figure 1

The Effect of Threading Dislocation on Current-Voltage Characteristics of 3.3 kV 4H-SiC Schottky Barrier Diode

We investigated the relationship between threading dislocation and current-voltage (I-V) characteristics of 3.3 kV 4H-SiC Schottky barrier diodes (SBDs). The crystal defects were observed using non-destructive methods. X-ray topography (XRT) and electron beam induced current (EBIC) were used to compare the current-voltage characteristics of fabricated SBDs with defects. The surface and process defects were found to be fatal to devices performance such as ideality factor and leakage current increased and the breakdown deterioration. However, the threading dislocations rarely affected forward I-V characteristics and blocking voltage of fabricated 3.3 kV SBDs. The leakage current of the SBDs with threading dislocations in active region was increased by 103 compared with those of the SBDs without defect.

A Novel 1.2 kV 4H-SiC Buffered-Gate (BG) MOSFET: Analysis and Experimental Results

A novel 1.2-kV-rated 4H-SiC buffered-gate MOSFET (BG-MOSFET) structure is proposed and experimentally demonstrated to have superior high frequency figures-of-merit (HF-FOMs) for the first time. From the measured data on devices fabricated in a 6-in foundry, the BG-MOSFET is demonstrated to have $4.0\times $ and $2.6\times $ smaller HF-FOM [ ${R}_{ {\scriptscriptstyle{\text {ON}}}}\times {Q}_{\text {gd}}$ ], and $3.6\times $ and $2.1\times $ smaller HF-FOM [ ${R}_{ {\scriptscriptstyle{\text {ON}}}}\times {C}_{\text {gd}}$ ], when compared with the conventional MOSFET and split-gate MOSFET, respectively.

Suppression of Punch-Through Current in 3 kV 4H-SiC Reverse-Blocking MOSFET by Using Highly Doped Drift Layer

Low on-resistance 4H-SiC reverse-blocking (RB) metal–oxide–semiconductor field-effect transistors (MOSFETs) have been developed by adopting a non-punch-through (NPT) drift layer in order to suppress the punch-through (PT) current under the reverse-blocking condition. The n-type NPT drift layer was 40- ${\mu }\text{m}$ thick doped to $3.7\times 10^{15} $ cm−3. The forward and reverse breakdown voltages of the fabricated NPT RB MOSFET were 3.6 kV and −3.0 kV, respectively. The differential specific on-resistance was 13.5 $\text{m}\Omega \cdot $ cm2 at room temperature, which was 33% lower than that of a 3 kV PT RB MOSFET, demonstrating superiority of the developed NPT RB MOSFET as a high-performance bidirectional switch.

Short-Circuit Degradation of 10-kV 10-A SiC MOSFET

The short-circuit behavior of power devices is highly relevant for converter design and fault protection. In this paper, the degradation during short circuit of a 10-kV 10-A 4H-SiC MOSFET is investigated at 6 kV dc-link voltage. The study aims to present the behavior of the device during short-circuit transients as it sustains increasing short-circuit pulses during its lifetime. As the short-circuit pulse length increases, degradation of the device can be observed in periodically performed characterizations. The initial degradation seems to be associated with the channel region, and continuous stressing leads to an overall increase in device on-state resistance at the end of the degradation study. Thermal simulation shows that the surface aluminum metalization reached its melting temperature and the top part of the device reaches temperatures above the rated junction temperature. Scanning electron microscope investigation shows aluminum reconstruction and cavities at the contact interface between the aluminum surface metalization and source contacts.

Electrical Characteristics of 10-kV 4H-SiC MPS Rectifiers with High Schottky Barrier Height

This paper reports the study of the fabrication and characterization results of 10-kilo-volt (kV) 4H-SiC merged PiN/Schottky rectifiers. A metal contact process was developed to make the Schottky contact on n-type SiC and ohmic contact on p-type SiC at the same time. The diodes with different Schottky contact width were fabricated and characterized for comparison. With the improvement quality of the Schottky contact and the passivation layer, the devices show low leakage current up to 10 kV. The on-state characteristics from room temperature to elevated temperature (423 K) were demonstrated and compared between structures with different Schottky contact width.

Injection modulation of p+–n emitter junction in 4H–SiC light triggered thyristor by double-deck thin n-base**Project supported by the National Natural Science Foundation of China (Grant No. 51677149)

To overcome hole-injection limitation of p+–n emitter junction in 4H–SiC light triggered thyristor, a novel high-voltage 4H–SiC light triggered thyristor with double-deck thin n-base structure is proposed and demonstrated by two-dimensional numerical simulations. In this new structure, the conventional thin n-base is split to double-deck. The hole-injection of p+–n emitter junction is modulated by modulating the doping concentration and thickness of upper-deck thin n-base. With double-deck thin n-base, the current gain coefficient of the top pnp transistor in 4H–SiC light triggered thyristor is enhanced. As a result, the triggering light intensity and the turn-on delay time of 4H–SiC light triggered thyristor are both reduced. The simulation results show that the proposed 10-kV 4H–SiC light triggered thyristor is able to be triggered on by 500-mW/cm2 ultraviolet light pulse. Meanwhile, the turn-on delay time of the proposed thyristor is reduced to 337 ns.

3.3 kV 4H-SiC JBS diodes with single-zone JTE termination

This paper reports the detailed design, fabrication and characterization of 3300V 4H-SiC junction barrier Schottky (JBS) diodes. It features an n-type epilayer with thickness of 33μm and doping concentration of 3×1015cm−3 and a single-zone junction termination extension (JTE) termination. The structure of drift layer, active region, and JTE are designed and optimized. Based on simulation and optimization results, the 4H-SiC JBS diodes are fabricated. The experimental results demonstrate that the optimized devices have a forward voltage drop of less than 1.8V at current level of 30A and a reverse breakdown voltage of about 4000V.