kV 4H-SiC Research Articles

Investigation into Short-Circuit Ruggedness of 1.2 kV 4H-SiC MOSFETs

The shout-circuit ruggedness of prototype 1.2kV SiC MOSFETs has been investigated. The short-circuit measurements were carried out at 25 °C and 125 °C with a dc bus voltage of 800 V and an on/off state gate voltage of +20/-10 V. The small difference in tfail between 25 °C and 125 °C indicates that the destructive breakdown occurs at temperatures much higher than 125 °C. The temperature at destructive breakdown estimated from the Wunsch-Bell formula is about 1400 °C. At such high temperatures, intrinsic carriers are increased markedly and generated heat leads to the destructive breakdown. tfail of all the SiC-MOSFETs studied is longer than 10 μs, meaning that the short-circuit ruggedness satisfies system requirements. These results show that the SiC-MOSFETs are promising for power electronics applications.

12 kV 4H-SiC p-IGBTs with Record Low Specific On-Resistance

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

Bevel Mesa Combined with Implanted Junction Termination Structure for 10 kV SiC PiN Diodes

A 10 kV 4H-SiC PiN diode with an improved junction termination structure has been fabricated. An improved bevel mesa structure, nearly vertical side-wall at the edge of pn junction and rounded corner at mesa bottom, has been formed by reactive ion etching (RIE). The junction termination extension (JTE) region has been optimized by device simulation, and simulated breakdown voltage has been compared with experimental results. The locations of electric field crowding and diode breakdown have been discussed.

On-State and Switching Performance of High-Voltage 15 – 20 kV 4H-SiC DMOSFETs and IGBTs

We compare the on-state and switching performance of high-voltage 4H-SiC n-channel DMOSFETs and p-channel IGBTs within a three-dimensional parameter space defined by blocking voltage, switching frequency, and current density. We determine the maximum current density each device can carry at a given switching frequency, such that the total power dissipation is 300 W/cm2. The IGBT current depends strongly on lifetime in the NPT buffer layer, and only weakly on lifetime in the drift layer. The MOSFET current is essentially independent of frequency.

A 10-kV Large-Area 4H-SiC Power DMOSFET With Stable Subthreshold Behavior Independent of Temperature

This paper presents the development and demonstration of large-area 10-kV 4H-SiC DMOSFETs that maintain a classically stable low-leakage normally off subthreshold characteristic when operated at les200degC. This is achieved by an additional growth (epitaxial regrowth) of a thin epitaxial layer on top of already implanted p-well regions in conjunction with a N20-based gate oxidation process. Additionally, the design space of the DMOSFET structure was explored using analytical and numerical modeling together with experimental verification. The resulting 0.15-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active 0.43-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die DMOSFET with 10-kV breakdown provides I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 8 A at a gate field of 3 MV/cm, along with a subthreshold current at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V that decreases from 1 muA (6.7 muA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at 25degC to 0.4 muA (2.7 muA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at 200degC.

Comparisons of Design and Yield for Large-Area 10-kV 4H-SiC DMOSFETs

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm2 of active area on a 1-cm2 die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs.

Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes

Designing and fabrication of 10-kV 4H-SiC PiN diodes with an improved junction termination structure have been investigated. An improved bevel mesa structure and a single-zone junction termination extension (JTE) have been employed to achieve a high breakdown voltage (ges 10 kV). The improved bevel mesa structure, nearly a vertical sidewall at the edge of the p-n junction and a gradual slope at the mesa bottom, has been fabricated by reactive ion etching. The effectiveness of the improved bevel mesa structure has been experimentally demonstrated. The JTE region has been optimized by device simulation, and the JTE dose dependence of the breakdown voltage has been compared with experimental results. A 4H-SiC PiN diode with a JTE dose of 1.1 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> has exhibited a high blocking voltage of 10.2 kV. The locations of electric field crowding and breakdown are also discussed.

Characterization, Modeling, and Application of 10-kV SiC MOSFET

Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mm2 SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10-kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications.

Influence of Shockley Stacking Fault Expansion and Contraction on the Electrical Behavior of 4H-SiC DMOSFETs and MPS diodes

ABSTRACTThe forward voltage drop (Vf) increase observed in 4H-SiC bipolar devices such as pin diodes due to recombination-induced Shockley stacking fault (SSF) creation and expansion has been widely discussed in the literature. It was long believed that the deleterious affect of these defects was limited to bipolar devices. However, it was recently reported that forward biasing of the body diode of a 10kV 4H-SiC DMOSFET led to similar Vf increases in the body diode I-V curve as well as a corresponding degradation in the majority carrier conduction characteristics as well and this degradation was believed to be due to the creation and expansion of SSFs during the body diode forward biasing. Here we report measurements comparing the influence of similar stressing, along with annealing and current-induced recovery experiments in DMOSFETs and merged pin-Schottky diodes with the previously reported results of these experiments in 4H-SiC pin diodes. The results of these experiments provide sufficient support that the observed degradation in the majority carrier conduction characteristics is the result of SSF expansion.

Degradation of Majority Carrier Conductions and Blocking Capabilities in 4H-SiC High Voltage Devices due to Basal Plane Dislocations

ABSTRACTThis paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, 10 kV 4H-SiC MPS (Merged PiN Schottky) diodes have been fabricated on a standard wafer and a low BPD (Basal Plane Dislocation) wafer, and their IV characteristics were evaluated before and after a forward bias stress, which resulted in minority carrier recombination and conductivity modulation in the drift epilayer of the diodes. After the stressing, the diode fabricated on standard wafer showed a significant increase in forward voltage drop, as well as a marked increase in leakage current, which were due to induction of stacking faults. The diode on the low BPD wafer showed very little change after the stress because the induction of stacking faults was minimized. Similar results were also observed on a 10 kV 4H-SiC DMOSFET. The results suggest that recombination-induced stacking faults are detrimental to all device types, and injection of minority carriers in majority carrier devices should be avoided at all times.

Analysis of Novel Packaging Techniques for High Power Electronics in SiC

A novel high temperature wire bondless packaging technique is numerically investigated in this paper. Extraction of device effective resistivity with temperature from numerical characteristics of 1.2kV 4H-SiC MOSFETs at a current density of 400A/cm2 have demonstrated a T−2 temperature dependence. Electro-thermal finite element analysis (FEA) of 1.2kV 4H-SiC MOSFETs sandwiched between two etched direct-bonded-copper substrate tiles has been performed. The thermal resistance of the ceramic sandwich package shows a 75% reduction in thermal resistance compared to conventional wire bonded assemblies. Mechanical analysis of the assembly has been used to investigate the residual stresses in the SiC dies at room temperature, which are then alleviated at higher temperatures during device operation. Mismatch of the expansion coefficients of the auxiliary materials in the assembly result in elevated stresses at full load operation, however these are well below the tensile strength of the respective materials and hence do not compromise the mechanical integrity of the package.

Progress on the Development of 10 kV 4H-SiC Pin Diodes for High Current/High Voltage Power Handling Applications

The development of 4H-SiC PiN diodes capable of blocking to greater than 10 kV while having current ratings of 20 A at 100 A/cm2 is continuing in earnest. VF instability of these diodes continues to be a roadblock, but progress is being made, and a 20 A/10 kV 4H-SiC PiN diode wafer with an overall device yield of 40% has been fabricated. The latest device characteristics are discussed, along with details of approaches in improving the reverse recovery characteristics of these diodes to satisfy the requirements needed for implementation into high voltage inverter modules capable of switching at up to 20 kHz.

Current gain of 4H–SiC high-voltage BJTs at reduced temperatures

The dependences of the common-emitter current gain β on the collector current IC have been measured at reduced temperatures in 3 kV 4H–SiC epitaxial-emitter npn bipolar junction transistors with implanted p+ base contact and base–emitter distances Lbe ranging from 3 to 15 µm. The collector–emitter voltage was fixed (at 100 V) to provide the active operation mode at any collector current in a wide range from 80 mA to 10 A (current densities of 3.5–445 A cm−2). The maximum current gain steadily grows with Lbe from 8 (Lbe = 3 µm) to 21 (Lbe = 15 µm) at room temperature. For all values of Lbe, β steadily increases as the temperature becomes lower; however, the smaller Lbe is, the weaker the effect produced by temperature lowering. As, for example, the temperature is lowered to −42 °C, β increases from 8 to 9 for structures with Lbe = 3 µm and from 21 to 31 for structures with Lbe = 15 µm. The phenomena observed have been accounted for by recombination at the p+–p base boundary.

Evolution of Drift-Free, High Power 4H-SiC PiN Diodes

The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching with less reverse recovery charge than commercially available Si PiN diodes. The path to commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a fundamental problem with the forward voltage stability resulting from stacking fault growth emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the progress toward producing stable high power devices with sufficient yield to promote commercial interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in reducing the BPD density and enhancing the forward voltage stability while being compatible with conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device yield (forward, reverse, and forward drift yields) from 0% to &gt;20%. The LBPD1 process appears to be more robust in terms of long term forward voltage stability.

Performance Comparison of 1.5kV 4H-SiC Buried Channel and Lateral Channel JBS Rectifiers

We theoretically and experimentally compare the performance of a new JBS rectifier structure, the Buried Channel JBS (BC-JBS) rectifier, with that of the Lateral Channel JBS (LC-JBS) rectifier with 1.5kV blocking capability in 4H-SiC. The BC-JBS rectifier employs buried p-type regions to create a vertical JFET region to reduce the surface electric field at Schottky contact during reverse blocking while the LC-JBS rectifier adds a lateral channel together with the vertical JFET region to protect the surface Schottky interface during high-voltage blocking conditions. The LC-JBS rectifier offers low reverse leakage current while the BC-JBS rectifier demonstrates lower specific on-resistance. The optimized LC-JBS rectifiers show low forward drop (&lt;1.8V) with PiN-like reverse characteristics.

High Current 6 kV 4H-SiC PiN Diodes for Power Module Switching Applications

Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

4.3 kV 4H-SiC merged PiN/Schottky diodes

The design, fabrication and characterization of high-voltage 4H-SiC merged PiN/Schottky (MPS) diodes operating close to the avalanche limit are presented. With a blocking voltage (VB) of 4.3 kV and a specific on-resistance (Ron) of 20.9 mΩ cm2, the figure-of-merit (FOM), equal to V2B/Ron, is 885 MW cm−2. Both the blocking voltage and FOM are among the highest levels reported to date. The trade-off between forward conduction and reverse leakage is experimentally investigated to analyse the optimum range of Schottky spacing.

DV/dt effect in high-voltage 4H-SiC thyristors

The switching of high-voltage (1.5 kV) 4H-SiC thyristors by the dV/dt effect has been investigated for the first time in the temperature range from 300 to 504 K. At a rise time of the forward bias V(t) equal to 30 ns, the characteristic bias at which the structure under investigation can be switched on by the dV/dt effect decreases steadily from 289 V at room temperature (dV/dt ∼ 9.7 kV µs−1) to 137 V at T = 504 K. The characteristic value of the critical charge per unit area, Qcr, is ∼1.9 × 10−7 C cm−2 at room temperature and also decreases steadily as the temperature increases.

Comparison of High-Voltage 4H-SiC Insulated-Gate Bipolar Transistor (IGBT) and MOS-Gated Bipolar Transistor (MGT)

In this paper, the performance of high-voltage (10kV) 4H-SiC n- and p-channel IGBTs and n-channel MOS-Gated Bipolar Transistor (MGT) are investigated and compared using 2- dimensional numerical simulations. We have found that the MGT in SiC is not suitable for applications at high blocking voltages and the p-channel IGBT is a better choice because of a much higher conductivity modulation in the drift region.

8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

The dependence of forward voltage degradation on crystal faces for 4H-SiC pin diodes has been investigated. The forward voltage degradation has been reduced by fabricating the diodes on the (000-1) C-face off-angled toward &lt;11-20&gt;. High-voltage 4H-SiC pin diodes on the (000-1) C-face with small forward voltage degradation have also been fabricated successfully. A high breakdown voltage of 4.6 kV and DVf of 0.04 V were achieved for a (000-1) C-face pin diode. A 8.3 kV blocking performance, which is the highest voltage in the use of (000-1) C-face, is also demonstrated in 4H-SiC pin diode.