Design Optimization of 1.2kV 4H-SiC Trench MOSFET

Abstract

In a trench MOSFET structure, p+ trench bottom implant (also called p+ shielding region) is commonly used to protect the gate oxide from high electric field stress, however, if the design and fabrication process are not optimized properly, the p+ shielding region together with n-drift and the p-base region will form a parasitic JFET which severely degrades the on-state performance of the device. This paper presents this parasitic JFET effect with experimental results and the optimization work that has been done to eliminate the parasitic JFET.