Keep-out Zone Research Articles

Convex optimization of stochastic path-constrained trajectories near asteroids

The environment around asteroids is of significant uncertainties, which could cause great challenges of exploration missions to asteroids. This paper presents a novel approach to stochastic optimal problem in path-constrained trajectory optimization near asteroids based on convex approach. The path constraints that prevent the spacecraft from colliding with asteroid in different scenarios are composed of keep-out zone constraint and glide-slope constraint, which are formulated in chance-constraint forms due to the uncertain state. To convexify these constraints, the first-order Taylor expansion is applied for linearization and the nonconvexity is tackled with the introduction of additional intermediate variable and virtual buffer. Thereafter, a convex optimization based method is proposed to solve stochastic optimal problem. The effectiveness of the proposed method is validated through simulations of soft landing and hopping transfer scenarios near irregular-shaped asteroid 1996HW1. The results indicate that the proposed method can generate path-constrained trajectories under uncertainties using convex optimization.

Long-Term Fuel-Optimal Collision Avoidance Maneuvers with Station-Keeping Constraints

This work presents a sequential convex program method to compute fuel-optimal collision avoidance maneuvers for long-term encounters. The low-thrust acceleration model is used to account for the control, but the method can compute high-thrust maneuvers by increasing the maximum available acceleration. Dealing with the long-term conjunction poses additional challenges compared to the short-term problem because the encounter is not instantaneous. Thus, under the assumption of Gaussian statistics, the probability of collision is replaced by a simpler metric, the instantaneous probability of collision (IPoC), and a keep-out zone constraint is formulated as a continuous condition to be respected throughout the time frame of interest. The robustness of the solution is improved by introducing a constraint on the sensitivity of IPoC. Furthermore, the collision avoidance problem is coupled with the classical station-keeping requirement for geostationary Earth orbit satellites and with a return to the nominal orbit condition for low Earth orbit satellites. Even though no guarantee is given for the recovery of the global optimum solution, numerical simulations in different orbital regimes show that the proposed approach can yield a local fuel-optimal solution with a run time suitable for autonomous applications.

Digital twin-driven smelting process management method for converter steelmaking

AbstractThe converter is an indispensable key equipment in the steel manufacturing industry. With the increasing demand for high-quality steel, there is an increasing demand for monitoring and controlling the status of the converter during the smelting process. Compared to other manufacturing industries, such as food processing and textile, converter steelmaking requires a larger keep-out zone due to its ultra-high temperatures and harsh smelting environment. This makes it difficult for personnel to fully understand, analyze, and manage the smelting process, resulting in low production efficiency and the inability to achieve consistently high-quality results. Aiming at the low virtual visualization level and insufficient monitoring ability of the converter steelmaking process, a process management method based on digital twin technology is proposed. Firstly, a digital twin system framework for full-process monitoring of converter steelmaking is proposed based on the analysis of the process characteristics of converter steelmaking. The proposed framework provides critical enabling technologies such as point cloud-based digital twin model construction, visual display, and steel endpoint analysis and prediction, to support full-process, high-fidelity intelligent monitoring. After conducting experiments, a digital twin-driven smelting process management system was developed to manage the entire smelting process. The system has proven to be effective as it increased the monthly production capacity by 77.7%. The waste of smelting materials has also been greatly reduced from 34% without the system to 7.8% with the system. Based on these results, it is evident that this system significantly enhances smelting efficiency and reduces both the costs and waste associated with the process.

Low Stress TSV Arrays for High-Density Interconnection

In three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W–TSV) is presented and developed. The hollow structure provides space for the release of thermal stress. Simulation results showed that the hollow W–TSV structure can release 60.3% of thermal stress within the top 2 μm from the surface, and thermal stress can be decreased to less than 20 MPa in the radial area of 3 μm. The ultra-high-density (1600 TSV∙mm−2) TSV array with a size of 640 × 512, a pitch of 25 μm, and an aspect ratio of 20.3 was fabricated, and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances. The average resistance of the TSV was 1.21 Ω. The leakage current was 643 pA and the breakdown voltage was greater than 100 V. The resistance change is less than 2% after 100 temperature cycles from −40 to 125 °C. Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W–TSV was 31.02 MPa, which means that there was no keep-out zone (KOZ) caused by the TSV array. These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.

Model predictive control for close-proximity maneuvering of spacecraft with adaptive convexification of collision avoidance constraints

This study investigated model predictive control (MPC) for close-proximity maneuvering of spacecraft. It is essential for a designed MPC to effectively handle collision avoidance between the servicer spacecraft and the client spacecraft, especially while the client is rotating. The rotating motion of the client leads to dynamic changes in the collision avoidance constraints, which increases the difficulty of optimizing the control input in the MPC framework. Therefore, this study presents a method to improve the performance and computational efficiency of MPC for rendezvous and docking with a nonrotating or rotating client. An ellipsoid is adopted to model the client’s keep-out zone (KOZ). Given the spherical KOZ of the servicer, an expanded ellipsoid is introduced to describe the KOZ for the center of mass of the servicer and modeled as a nonlinear constraint. The linearization method for reference points located at the expanded ellipsoid is adopted to convexify the nonlinear constraints. The reference points are adaptively determined according to the positions of the servicer, client, and expanded ellipsoidal KOZ. The resulting hyperplanes are then used to describe the collision avoidance constraints. By utilizing the aforementioned strategies, combined with the calculated reference points, an adaptive convex programming algorithm suitable for real-time implementation of MPC is derived. The performance of the proposed method is demonstrated through numerical simulations.

Risk-Aware Path Planning for Unmanned Aerial Systems in a Spreading Wildfire

Path planning for small unmanned aerial systems (SUAS) in the presence of poorly understood and dynamic obstacles is a challenging problem: for example, flight over a spreading wildfire. Evidential information fusion is used to estimate the current wildfire state and the resulting heat aura at flight level. This approach accounts for ignorance, which is a result of conflict among sensors operating in a harsh environment and a computational forecasting agent that uses a fire evolution model of inadequate accuracy. An SUAS is employed to visit locations of high conflict to provide additional situational awareness. Flight-level heat aura is modeled as a keepout zone with probabilistic boundaries for SUAS path planning. A novel unsupervised classification algorithm is developed to identify distinct obstacle boundaries within the estimated heat aura. Path planning is posed as a chance-constrained optimal control problem, which is transcribed to a nonlinear program via pseudospectral discretization. The results show that this approach can yield a family of solutions that elicit the risk associated with each mission design, and the appropriate choice of risk can aid in the generation of “keyhole paths.”

Evaluation of Cost-Effective Flexible High-Speed Data Exchange Links for Heterogeneously Integrated Multi-Chip Modules and Boards

With increasing complexity and heterogeneity, miniaturized integrated system on both multi-chip module and printed circuit board levels relies more and more on high-speed point-to-point serial signal transmission links as the backbone of inter-chip data signal exchange network, which are inevitably accompanied by signal integrity problems such as loss, reflection, and crosstalk. The difficulties in the physical design phase of interconnect routing for high-speed link on densely occupied package interposers or printed circuit boards and the associated planar area overhead (keep-out zone for the crosstalk prevention and impedance matching, etc.), as well as the relevant cost in manufacturing, performance analysis and actual measurement or evaluation, are also sharply increasing; furthermore, the interconnects implemented on interposer or printed circuit board substrate are physically inflexible, and the corresponding microsystems are not suitable for emerging applications that generally demand good deformability and good conformality to 3-dimensionally shaped mounting surface. How to simultaneously elevate the cost-effectiveness, signal transmission performance and physical flexibility of the high-speed link, while keeping low profile of the whole module, has become one of the major challenges in the evolution of micro/nano system technology. Accordingly, this paper proposes a cable-based point-to-point link method, which adopts physically flexible and widely available off-the-shell cables that can be assembled onto the surface of the interposers or boards as a potential cost-effective solution to the challenge mentioned above. Universal Serial Bus, micro-coaxial cables, and Twinax cables are explored as candidates. The full links for each cable, from one of the paired connectors to another, are physically modeled and validated by an electromagnetic full-wave structural simulation tool, with key components of each type of link taken into considerations. The simulated results and the measured results from vector network analyzers are compared, which verifies the effectiveness of our proposal.

Online collision avoidance trajectory planning for spacecraft proximity operations with uncertain obstacle

The spacecraft relative motion trajectory planning is one of the enabling techniques for autonomous proximity operations, especially in the increasingly complicated mission environments. Most traditional trajectory planning methods focus on improving the performance criteria in the deterministic conditions, whereas various uncertain elements in practice would significantly degrade the trajectory performance. Considering the uncertainties underlying the collision avoidance constraints, this paper suggests a model predictive control based online trajectory planning framework in which the obstacle information in higher-precision would be consistently updated by the onboard sensor. To improve the computational efficiency of the online planning framework, the rotating hyperplane (RH) technique is utilized to transform the nonlinear ellipsoidal keep-out zone constraints into convex formulations. And the concept of rotation window is introduced to eliminate the unexpected mismatch between the spacecraft motion and hyperplane rotation in the conventional RH method, which in sequence improves the RH method’s capability for multiple obstacle avoidance problem. Moreover, a three-dimensional (3-D) extension strategy is proposed to simplify the computation procedure when applying the RH method for a 3-D collision avoidance problem. Numerical simulations are carried out to validate the performance of the proposed online trajectory planning framework in addressing the uncertain collision avoidance constraints.

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique.

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

Vertical traversal approach towards TSVs optimisation over multilayer network on chip (NoC)

In symmetric 3-D chip stacking, TSVs plays an important role and provides denser and fine pitches. The number of vertical links in 3-D mesh NoC topology is equal to 2(N−(N23)), where N is the number of network nodes. The TSVs use pads for establishing a connection between the layers, which could generate the misalignment issue due to chip warpage, thermal stress, and TSVs cross-coupling, which notifies a maximum permitted density of TSVs Keep-Out Zone. The study has discussed the analytical model of the seven-port router to express an average number of packets at equilibrium conditions for the physical and virtual channel and demonstrated the performance model. The latency objective function is deduced over reduced global interconnect and algorithm proposed for adaptive XYZ routing, in support of TSV placement scheme. Later the analytical model is emulated for practical significance.

Collision-Free Trajectory Design for Long-Distance Hopping Transfer on Asteroid Surface Using Convex Optimization

The irregular shapes and gravitational fields of asteroids challenge the design of collision-free asteroid surface hopping trajectories. A novel collision-free long-distance transfer trajectory design algorithm based on the convex optimization is presented in this article. A combinatorial keepout zone consisting of three spheres is defined to avoid the spacecraft colliding with the asteroid surface during the transfer. The boundary of the keepout zone is close to the surface of the target asteroid. With the Taylor expansion approximation, the nonconvex keepout zone constraint becomes convex. Two convex glide-slope constraints are employed for avoiding colliding during the ascent and descent. Thereafter, a convex optimization problem for solving a collision-free long-distance transfer trajectory between arbitrary two surface points is formulated. Moreover, an ant colony optimization algorithm combined with the proposed method is used to solve the optimal hopping sequence problem for exploring multiple points on the asteroid surface. Finally, several numerical simulation examples for the asteroid 433 Eros validate the feasibility and effectiveness of the algorithm.

Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs

Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneous 3D-ICs. TSV-induced channel length directional stress ( $S_{ZZ}$ ) predominantly causes variations of on-state current ( $\Delta I_{on}$ ). NSFETs exhibit the greater $\Delta I_{on}$ than FinFETs because electron velocities and densities in channels vary with respect to $S_{ZZ}$ in the same directions for NSFETs but do the opposite for FinFETs. Nevertheless, TSV-induced mechanical stress is negligible when TSV is farther than keep-out zone. Meanwhile, TSV signals can be coupled to operating devices through substrate and induce capacitive and back-bias noise coupling currents ( $I_{cap}$ , $I_{b-b}$ ). NSFETs exhibit the greater $\vert I_{cap}\vert /I_{on}$ than FinFETs because its wider source/drain (S/D) epitaxies form larger depletion capacitances between drain and punch-through stopper (PTS). On the other hand, the $\vert I_{b-b}\vert /I_{on}$ is smaller for NSFETs because its parasitic bottom transistor alleviates back-bias-induced potential barrier lowering. Furthermore, wide diameter of Cu of TSV increases $\vert I_{b-b}\vert /I_{on}$ only, but short rise time of TSV signals increases both $\vert I_{cap}\vert /I_{on}$ and $\vert I_{b-b}\vert /I_{on}$ . Unfortunately, conventional devices cannot satisfy criterion for analog applications ( $\vert I_{cap}$ , $I_{b-b}\vert /I_{on} %); therefore, a new strategy inserting bottom oxide (BOX) beneath the S/D with undoped PTS is suggested. The $\vert I_{cap}\vert /I_{on}$ for NSFETs decreases by undoped PTS, but not for FinFETs due to a remnant depletion capacitance between fin and PTS. The $\vert I_{b-b}\vert /I_{on}$ for NSFETs decreases remarkably due to completely blocked $I_{b-b}$ path, but FinFETs still have $I_{b-b}$ path under the fin. Therefore, NSFETs with BOX and undoped PTS are the most suitable for sub 5-nm node heterogeneous 3D-IC, especially in analog applications.

Electrochemical Behavior of 2M5S and Its Influence on Reduction of Cu Pumping and Keep-Out Zone

Previously, we have reported the low thermal expansion copper electrodeposited in solution containing 2-Mercapto-5-benzimidazolesulfonic acid sodium salt dihydrate (2M5S). In this research, we investigated the electrochemical behavior 2M5S additive by CVS and LSV measurements. The 2M5S additive showed an inhibition effect during electrodeposition of copper, both in the absence and presence of Cl−. Using a combination of the 2M5S leveler with another SDDACC leveler and SPS accelerator, the thermal expansion of copper was reduced and the TSV was filled without defects. The SEM results showed that the copper pumping height of low TEC copper in PECVD SiO2 TSV was only 0.5 μm. Meanwhile, the copper pumping height of reference conventional copper in PECVD SiO2 TSV was about 2 μm. Furthermore, compared with thermal stress curve in Si around the conventional copper TSV, thermal stress curve in Si around the low TEC copper TSV was much lower and the KOZ also was reduced to about 1 μm.

Modeling Copper Plastic Deformation and Liner Viscoelastic Flow Effects on Performance and Reliability in Through Silicon Via (TSV) Fabrication Processes

Copper plastic deformation and liner viscoelastic flow effects on performance and reliability are studied for TSV-middle and backside TSV-last fabrication processes. Incremental plasticity model with nonlinear hardening and Maxwell viscoelasticity model are employed to characterize TSV copper and liner dielectrics material behaviors. The model parameters are chosen to match experimental data. It is found that both plastic deformation in copper and viscoelastic flow in dielectrics affect the trade-off between TSV keep-out-zone (KOZ) size and TSV extrusion. The backside TSV-last process generates less residual stresses and mobility changes in active silicon than the TSV-middle process, and avoids M1 metal resistance increase due to TSV extrusion at elevated process temperatures. The TSV plastic deformation and liner viscoelastic flow effects on residual stresses and reliability in M1 interconnects and dielectrics are also examined for two different M1 configurations.

E-field induced keep-out zone determination method of through-silicon vias for 3-D ICs

An increase in the number of the through‑silicon vias (TSVs) per unit area causes the electrical channel in neighboring semiconductor devices to be closer to the depletion region induced by the electric-field (E-field) around the TSV. A keep-out zone (KOZ) is required to ensure the proper operation of three-dimensional integrated circuits (3-D ICs) using TSVs given these negative effects. The proposed method with which to determine the KOZ for 3-D ICs includes procedures for extracting the charges produced during the TSV formation process and for calculating the depletion region from a nonlinear metal-oxide-semiconductor (MOS) capacitance model. The results of a comparison of the proposed method with a previous method show that the charge carriers in the depletion region and charge-type imperfections of in TSV must be considered for an accurate KOZ.

A Effect of Halide on Cobalt Electrodeposition for through-Silicon-Via(TSV) Application

The size of integrated circuit (IC) devices had gradually decreased. Because of limit to reduction, 3D interconnection technology had emerged. As one of the 3D interconnection technologies, Through Silicon Via (TSV) replaced conventional wire bond by making vertical electrical connections. TSVs could increase the device performance because TSV had advantages such as higher interconnection density, shorter length of interconnection, lower power consumption, and lower electrical resistance [1]. TSV was mainly plated with copper with low resistance and low electro-migration. However, copper annealing process, metal interconnect process and bonding process between chips and chips or wafers and wafers were performed at high temperature in BEOL, which causes problems such as thermal extrusion and keep-out zone. Thermal extrusion is enough to make the defect and crack at insulating layer or metal interconnect on TSV. And the keep-out zone could cause some degradation in device performance [3]. Therefore, Cobalt was used to fill TSV as alternative material which can reduce this problem because the CTE of cobalt was lower than that of copper. However, while many studies on copper TSV filling was reported, studies on cobalt TSV filling was insufficient. For the TSV bottom-up filling, TSVs were conventionally filled with some additives such as accelerator and suppressor by using the electrochemical deposition. In addition, halide was used to enhance adsorption of suppressor. Many studies confirmed effect of halide in copper electrodeposition [2, 4]. In this study, high-aspect ratio TSVs was filled with cobalt with suppressor as the single additive using the electrochemical deposition. The filling behavior was affected by suppressor concentration and the effect was saturated. In copper electrodeposition, halide ion is added because adsorption of suppressor is affected by chloride [2, 4]. Therefore, chloride, one of the halide, was added to confirm the effect of halide on cobalt electrodeposition. In cobalt electrodeposition, the role of chloride was different from that of copper electrodeposition. Electrochemical analysis explains the effect of chloride concentration in the cobalt filling. REFERENCES [1] Sanghyun Jin, Geon Wang, and Bongyoung Yoo, “ Through-Silicon-Via (TSV) Filling by Electrodeposition of Cu with Pulse Current at Ultra-Short Duty Cycle”, Journal of The Electrochemical Society, 2013, 160 (12) D3300-D3305 [2] Liu Yang, Aleksandar Radisic, Johan Deconinck, and Philippe M. Vereecken, “ Modeling the Bottom-Up Filling of Through-Silicon vias Through Suppressor Adsorption/Desorption Mechanism”, Journal of The Electrochemical Society, 2013, 160 (12) D3051-D3056 [3] Suk-Kyu Ryu, Kuan-Hsun Lu, Tengfei Jiang, Jang-Hi Im, Senior Member, Rui Huang, and Paul S. Ho, Fellow,“ Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 6, VOL. 12, NO. 2, 255-262 [4] Ning Xiao, Deyu Li, Guofeng Cui, Ning Lia, Qing Li, Gang Wu, “Adsorption behavior of triblock copolymer suppressors during the copper electrodeposition”, Electrochimica Acta, 116 (2014) 284– 291

Stress analysis of shielding electrode in chip with pressure sensor embedded in accelerometer

PurposeAnalysis of the thermal effects during the packaging process or in the actual operating environment is necessary to develop small monolithic integrated sensing chips with heterogeneous integration. The use of multiple layers and various materials in monolithic integrated sensing chips addresses the coefficient of thermal expansion (CTE) mismatch issue. The purpose of this study is to focus on the residual stress analysis of the shielding electrode, which is a metal film that prevents pull-in of proof-mass during anodic bonding in microelectromechanical system (MEMS) chips with pressure sensors embedded in an accelerometer.Design/methodology/approachThe finite element model of the chip was built by the commercial software ANSYS, and the residual stress was evaluated during the die attachment process for the shielding electrode. Various shielding electrode materials and a proposed design with a keep-out zone to reduce the residual stress are discussed, with a focus on the relationship between the geometric parameters of the chip and the residual stress for copper shielding electrodes of different thicknesses.FindingsThe results of the finite element analysis showed that the use of polysilicon as a shielding electrode in the proposed design generated the lowest residual stress because of its low CTE. The maximum stresses in both of in-plane and out-of-plane directions in the finite element model were reduced by keep-out zone design for the proposed design of the copper shielding electrode, and had 11 times reduction in out-of-plane direction especially, according to the nonlinear analysis as the stress concentration point in the shielding electrode moved. Moreover, the design with a thinner shielding electrode, thinner glass substrate and higher CTE of the glass substrate also lowered the maximum von Mises stress. On the other hand, the stress level during the operating temperature, without considering residual stress, overestimated up to five times in the proposed design.Originality/valueIn this study, valuable suggestions are proposed for the design of chips with pressure sensors embedded in accelerometers.

Model Predictive Control to Autonomously Approach a Failed Spacecraft

In this study, a model predictive control (MPC) method is developed for a servicer spacecraft autonomously approaching a tumbling failed spacecraft at an ultraclose range. Flight safety and collision avoidance are basic requirements during the approach. Two types of a failed spacecraft with complex configurations are considered, and a double-ellipsoid composite envelope strategy is designed to model their keep-out zones. Given the keep-out zone of the servicer, two expanded ellipsoids are subsequently introduced to determine the collision and sufficient conditions for collision avoidance are derived by using the form of concave constraint. The tumbling motion of the target is considered, and a CW-based translational dynamics and derived attitude dynamics of the target are formulated to predict the motion of the docking point and keep-out zone. The MPC is formulated to drive the servicer tracking the docking point with collision avoidance and handle constraints including control input saturation and relative velocity bound. Convexification of the collision avoidance constraint and sequential convex programming are adopted for the implementation of MPC. Scenarios on the servicer with different initial positions approaching the target with different angular velocities are simulated, and the simulation results indicate that the proposed MPC method is effective.

Elimination of Scallop-Induced Stress Fluctuation on Through-Silicon-Vias (TSVs) by Employing Polyimide Liner

3-D modeling of through-silicon-via (TSV) with sidewall scallops, combined with an element birth and death technique, is explored in finite-element analysis (FEA) in this paper to evaluate and improve the thermo-mechanical reliability. Compared with the classic FEA, the proposed modeling and simulation method takes into account the process sequence and, hence, can accurately characterize the stress distribution and fluctuation phenomenon of TSVs, which agrees pretty well with X-ray experimental data. In order to solve the stress fluctuation problem, the process-friendly polyimide dielectric liner is employed to replace the SiO2 liner, which smoothens the sidewalls, reduces the average stress values, and eliminates the local stress fluctuation. The average stress on TSVs with a polyimide liner along the silicon-liner interface and copper-barrier interface are both lower than TSVs with an SiO2 liner and the fluctuation magnitude is also dramatically decreased, which demonstrates that the TSV with a polyimide liner has higher reliability and lower risks in interfacial delamination. Furthermore, the keep-out zone size is also decreased by using a polyimide liner, which is beneficial to realize high-density 3-D integration.

Modeling and Performance Analysis of Shielded Differential Annular Through-Silicon Via (SD-ATSV) for 3-D ICs

A shielded-differential annular through-silicon via (SD-ATSV) is proposed and investigated. The equivalent circuit model is developed with the influence of the electrically floating silicon substrate taken into account. By virtue of the circuit model, the frequency- and time-domain electrical characterizations of the SD-ATSV are conducted. Furthermore, the thermo-mechanical stress of the SD-ATSV is captured and compared with that of the shielded-differential cylindrical through-silicon via. It is demonstrated that by utilizing the SD-ATSV, the keep-out zone can be reduced without performance degradation.