Junctionless Tunnel Field Effect Transistor Research Articles

Leakage current reduction in junctionless tunnel FET using a lightly doped source

In this paper, we explain the problem of dramatic OFF-state leakage in junctionless tunnel field effect transistor (JLTFET) for a channel thickness greater than 10 nm. In JLTFET, with channel width greater than 10 nm, the depletion region primarily remains confined below the dielectric–semiconductor interface. Hence, we tend to incur significant leakage through the center of the device. With the help of 2D device simulations, we demonstrate that the cause of the leakage current is predominantly due to thermal injection in the source region and is concentrated through the center of the device. We suggest a technique of using a lightly doped source region, below the p-gate to increase the barrier and prevent any leakage. The proposed alteration records an improved ION/IOFF ratio for JLTFET for a channel of width 20 nm.

Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor

We analyse a novel hybrid semiconductor field-effect transistor (FET), known as the junctionless tunnel FET (JL-TFET). We show that a parasitic bipolar transistor action, which is highly undesirable in conventional metal/oxide/semiconductor FETs and junctionless transistors, is the mechanism that activates the JL-TFET ON state. It is found that the sub-threshold slope (SS) in the JL-TFET is strongly dependent on the silicon thickness and a sub-60 mV/decade SS is observed for a thin silicon body only. We further study the JL-TFET design parameters as regards the effects of the control gate workfunction, P-gate workfunction, and isolation region on the JL-TFET characteristics.

Charge‐plasma‐based super‐steep negative capacitance junctionless tunnel field effect transistor: design and performance

A double-gate charge-plasma-based super-steep negative capacitance junctionless tunnel field effect transistor (NC-JLTFET) using a ferroelectric gate stack is proposed. Structurally, the NC-JLTFET consists of a heavily doped n-type silicon (Si) channel with two distinctive gates (control gate and fixed source gate). The fixed source gate accounts for the charge-plasma (hole plasma) formation which results in surrogate p-type doping by using work-function engineering. It induces a uniform p-region on the source side on the n-type doped Si film having a thickness less than the Debye length (L D). The key attribute of the NC-JLTFET is the ferroelectric gate stack which is employed as a control gate resulting in NC behaviour due to positive feedback among the electric dipoles in the ferroelectric material. The NC-JLTFET endeavours to achieve a super-steep sub-threshold slope, a paramount boost in drive current and a substantial enhancement in peak transconductance (g m) than the JLTFET. Meanwhile, it embraces the inherent advantages of the charge-plasma junctionless structure. Thus, it avails itself of a simple fabrication process flow and high immunity against process variations and random dopant fluctuations.

Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET

Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gate = 4.2 eV, gate1 = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10−6 A/μm, the off current remains as low as 9.1 × 10−14 A/μm. So ION/IOFF ratio of ≃ 108 is achieved. Point subthreshold swing has also been reduced to a value of ≃ 41 mV/decade for TiO2 gate material.

Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor

We propose a dynamic threshold voltage junctionless tunnel FET (DT-JLTFET) in which the threshold voltage can be dynamically adjusted, resulting in higher ON-current. Through 2D numerical simulations, it is presented that the threshold voltage in the DT-JLTFET can be adjusted by applying a voltage to the adjust gate. The impact of the threshold voltage shift on the overall performance of the device is also studied. A comparison is made between the dynamic threshold voltage characteristics of a silicon JLTFET and a Si0.7Ge0.3 source JLTFET.

Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors

This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain coupling to efficiently switch the TFETs, producing an abrupt on-off switching. Because of n-drain/p+body junction, the off-state tunnel barrier can be extended into the drain, ensuring an excellent short-channel effect without the limitation of channel lengths. Si/Ge heterojunctions and high-k gate insulators are combined with the AJ-TFETs for additional on-current boosting. Using compact structures and feasible parameters from practical Si-based CMOS technologies, the advancement in the on-off switching and short-channel effect make the AJ-TFET highly promising as an ideal approach into the sub-10-nm regimes.

Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Analog performance of double gate junctionless tunnel field effect transistor

For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor (DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field effect transistor (DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.

P-type double gate junctionless tunnel field effect transistor

We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor (P-DGJLTFET) and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material (TiO2) of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high ION of ∼0.3 mA/μm, a low IOFF of ∼30 fA/μm, a high ION/IOFF ratio of ∼1 × 1010, a subthreshold slope (SS) point of ∼23 mV/decade, and an average SS of ∼49 mV/decade at a supply voltage of −1 V and at room temperature, which indicates that P-DGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.

Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V semiconductor compound, indium aluminium arsenide. The analog performance parameters are extracted using device simulations and also compared with the Si JLTFET. We show that III–V JLTFET delivers much better performance parameters, in comparison to Si JLTFET, which includes transconductance generation efficiency (Gm/ID), intrinsic gain (GmRo) and unity gain frequency (fT) along with various gate capacitances.

Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III–V Semiconductor

Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III–V Semiconductor

Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I ON/I OFF.

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.

Junctionless Tunnel Field Effect Transistor

In this letter, a double-gate junctionless tunnel field effect transistor (JL-TFET) is proposed and investigated. The JL-TFET is a Si-channel heavily n-type-doped junctionless field effect transistor (JLFET), which uses two isolated gates (Control-Gate, P-Gate) with two different metal work-functions to behave like a tunnel field effect transistor (TFET). In this structure, the advantages of JLFET and TFET are combined together. The simulation results of JL-TFET with high-k dielectric material (TiO2) of 20-nm gate length shows excellent characteristics with high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio (~6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ), a point subthreshold slope (SS) of ~38 mV/decade, and an average SS of ~70 mV/decade at room temperature, which indicates that JL-TFET is a promising candidate for a switching performance.

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transist...