Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors

Abstract

This study presents a new asymmetric junctionless tunnel field-effect transistor (AJ-TFET) to scale TFETs into sub-10-nm regimes. The asymmetric junctionless p+ source/body and junctional n/p+ drain/body separately optimize the lateral source and drain coupling to efficiently switch the TFETs, producing an abrupt on-off switching. Because of n-drain/p+body junction, the off-state tunnel barrier can be extended into the drain, ensuring an excellent short-channel effect without the limitation of channel lengths. Si/Ge heterojunctions and high-k gate insulators are combined with the AJ-TFETs for additional on-current boosting. Using compact structures and feasible parameters from practical Si-based CMOS technologies, the advancement in the on-off switching and short-channel effect make the AJ-TFET highly promising as an ideal approach into the sub-10-nm regimes.