Junctionless Thin-film Transistors Research Articles

Junctionless Structure Indium-Tin Oxide Thin-Film Transistors Enabling Enhanced Mechanical and Contact Stability.

In recent years, considerable attention has focused on high-performance and flexible crystalline metal oxide thin-film transistors (TFTs). However, achieving both high performance and flexibility in semiconductor devices is challenging due to the inherently conductive and brittle nature of crystalline metal oxide. In this study, we propose a facile way to overcome this limitation by employing a junctionless (JL) TFT structure via oxygen plasma treatment of the crystalline indium-tin oxide (ITO) films. The oxygen plasma treatment significantly reduced oxygen vacancies in the ITO films, contributing to the significant reduction in the carrier concentration from 4.67 × 1020 to 1.39 × 1016. Importantly, this reduction was achieved without inducing any noticeable structural changes in the ITO, enabling the successful realization of ITO JL TFTs with an adjustable threshold voltage. Furthermore, the ITO JL TFTs demonstrate good stability and reliability under various bias stress conditions, aging in the air atmosphere, and high-temperature processes. In addition, the ITO JL TFTs exhibit low light sensitivity due to the wide bandgap of ITO and further suppression of Vo defects, making them suitable for applications requiring stable performance under light exposure. To compare and analyze the flexibility of the JL structure and conventional structure with additional source/drain (S/D) junction in ITO TFTs with nonencapsulation, we utilized mechanical simulations and transmission line method (TLM). By employing the JL structure in ITO TFT through carefully optimized oxygen plasma treatment, we successfully mitigated stress concentration at the S/D-channel interface. This resulted in a JL ITO TFT that exhibited a change in contact resistance of less than 20% even after 20,000 bending cycles. Consequently, a stable and flexible ITO TFT with field-effect mobility (μFE) of 12.74 cm2/(V s) was realized, outperforming conventionally structured ITO TFTs with additional S/D junction, where the contact resistance nearly tripled.

The Impact of an Extended Gate Field Plate on the DC and RF Characteristics of a Junctionless Thin-Film Transistor

In this work, conventional and drain offset junctionless (JL) finlike thin-film transistors (FinTFTs) with and without extended gate field plate (E-GFP) are fabricated. Drain offset JL FinTFTs showed a higher breakdown voltage than that of the conventional one. By extending the GFP over the drain offset region, holes were generated on the surface of the drain offset region that reduce drain resistance. Therefore, the drain offset JL FinTFT with E-GFP exhibited better on-current, breakdown, and high-frequency characteristics than the one without E-GFP. Results also show that all the noise spectral densities of various JL FinTFTs follow a 1/f trend and were similar in the studied frequency range.

Impacts of Independent Dual-Gate Operation on Reliability of Nanosheet Junctionless Thin-Film Transistor

In this work, impacts of the independent dual-gate (IDG) operation on performance and reliability of the polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) with a nanosheet channel (~4 nm) are investigated. Compared to the single-gate (SG) operation, the JL-TFT with tied dual gate (DG) operation times maximum transconductance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${G}_{m\_{}{\text {max}}}$ </tex-math></inline-formula> ) improvement and 3.3 times driving current enhancement. The tied DG operation also exhibits better gate bias stress immunity than the SG operation although the tied DG stress causes more serious damages to the JL-TFT than the SG stress. As for the independent back gate (BG) voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ) operation mode, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> can provide a wide threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) tuning range ~2 V when the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> is modulated from 0 to −4 V. The negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> bias stress would induce electron injection from the BG, resulting in positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift. Because the positive top gate voltage stress exhibits more serious electrical degradation than the negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> stress, using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to modulate the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFT will cause a slightly more serious reliability issue. The results show the feasibility of using independent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> to adjust the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> of the JL-TFTs to meet the multiple- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> requirement of advanced integrated circuits.

Flexible Transparent Electric-Double-Layer Junctionless Thin Film Transistors with Low Operating Voltage

Flexible transparent junctionless thin film transistors gated by microporous SiO2 dielectric with electric-double-layer (EDL) effect are fabricated onto PET substrates at room temperature. These devices exhibit high-performance n-type transistor characteristics operating in enhancement mode with low operating voltage of 1.5 V due to the huge gate specific capacitance (0.44 μF cm−2 at 40 Hz) related to EDL formation. The electron field-effect mobility of 28.4 cm2 V−1 s−1, current on/off ratio and the subthreshold swing are found to be 5 × 106 and 0.1 V decade−1, respectively. These achievements demonstrate that flexible transparent junctionless thin-film transistors are promising for the next-generation low-power flexible transparent electronics applications.

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Influence of Tunable Work Function on SOI-based DMG Multi-channel Junctionless Thin Film Transistor

Design and Analysis of IGZO Based Junctionless Thin Film Transistor Using SOI Technology

In this paper, IGZO based Junctionless Thin Film Transistor (IGZO JLTFT) using SOI technology is proposed with a channel length of 20 nm. The article also demonstrates a comparative analysis of amorphous Silicon-based JLTFT and artificial material IGZO based JLTFT using the Silvaco Atlas tool. Based upon the Junctionless properties, the compound, and high bandgap material, Indium Gallium Zinc Oxide (IGZO) is used to overcome the Short Channel Effects (SCEs) caused due to continuous miniaturization of the channel size. Optimization of the proposed SOI based IGZO JLTFT device has been carried out, by varying the Buried oxide and gate oxide materials and their thicknesses, and HFO2 has been demonstrated to give the best Ion/Ioff ratio. Further, gate metal work-function engineering is employed to enhance the performance of the proposed device in terms of increasing on-state current, and reducing off-state current. Through rigorous simulations with variations in different device parameters, it is demonstrated that the 20 nm IGZO JLTFT with HfO2 as Buried and Gate oxides, and work functions of 4.8 eV each for both metal gates, provides the best performance such as: Ioff of 9.97*10−12 A, threshold voltage of 0.38 V, overall gate capacitances of 1.13*10−15 F, and Subthreshold Slope (SS) of 93 mV/dec.

Impacts of Ammonia Gas Plasma Surface Treatment on Polycrystalline-Silicon Junctionless Thin-Film Transistor

The impacts of ammonia gas (NH3) plasma treatment on the performance and positive gate bias stress (PGBS) of polycrystalline-silicon (poly-Si) junctionless thin-film transistor (JL-TFT) are studied. A −0.785-V threshold voltage ( $V_{\mathrm {TH}}$ ) shift of JL-TFT due to the NH3 plasma treatment is observed, which is attributed to the fixed oxide charge effect of the plasma-induced interfacial layer (PIL). In addition, the transconductance of JL-TFT with the NH3 plasma treatment is enhanced by ~2.73 times due to the trap state passivation of grain boundaries in the poly-Si, and the ON-state current ( $I_{\mathrm {ON}}$ ) is enhanced by ~2.91 times. In addition to the performance enhancement of JL-TFT by the plasma process, the $V_{\mathrm {TH}}$ shift of poly-Si JL-TFT under PGBS is suppressed from −0.240 to −0.063 V after the plasma treatment. It is attributed to the less degradation of insulator/channel interface due to the growth of PIL by the plasma process. Moreover, the $I_{\mathrm {ON}}$ degradation of JL-TFT after PGBS is also improved from −19% to −16% after the plasma treatment. As the carrier transport of JL-TFT is the bulk conduction rather than the surface conduction of conventional inversion-mode TFT, the degradation of insulator/channel interface would exhibit less impacts on the $I_{\mathrm {ON}}$ . The improvement of performance and PGBS of JL-TFT by the NH3 plasma treatment would be beneficial to the application of 3-D integrated circuits.

Performance of Junctionless and Inversion-Mode Thin-Film Transistors With Stacked Nanosheet Channels

This article comprehensively investigated a junctionless thin-film transistor (JL TFT) with stacked nanosheet (NS) channels. Through experiments, we 1) compared a JL TFT with a single NS channel and a JL TFT with stacked NS channels and 2) compared an inversion-mode TFT with stacked NS channels and the JL TFT with stacked NS channels; the TFTs were fabricated using Si-based technology. The JL TFT with stacked NS channels exhibited a subthreshold slope of 135 mV/dec and drain-induced barrier-lowering value of 50.8 mVV−1, which were superior to those of the other devices. Furthermore, we simulated another device with a hybrid P/N/P channel structure based on the JL TFT by using three-dimensional technology computer aided design (3D TCAD) simulation. According to the study results, the JL TFT with stacked NS channels is a promising candidate for scaling down Si TFTs and for use in advanced 3D applications.

Dependence of Sub-Thermionic Swing on Channel Thickness and Drain Bias of Poly-Si Junctionless Thin-Film Transistor

We demonstrate the polycrystalline-silicon (poly-Si) junctionless (JL) thin-film transistor (TFT) with a planar structure and an ultra-thin channel film thickness ~1.5-nm exhibiting subthreshold swing (S.S.) less than 60 mV/decade. The S.S. of the poly-Si JL-TFT shows abnormal drain-voltage dependence, which the higher drain voltage leads to the smaller S.S. The minimum S.S. (S.S.min) observed in this letter is about 30 mV/decade, which is a record low S.S.min. The sub-60-mV/decade S.S. of the poly-Si JL-TFT is attributed to the impact ionization effect resulting from the high lateral electric field at the drain side at OFF-state. It is different from the conventional inversion-mode transistor, whose pinch-off point is observed at ON-state rather than the OFF-state. The lateral electric field is also found to be increasing with decreasing the channel thickness, and as a consequence, the impact ionization effect is more pronounced when the channel thickness is thinner. This letter shows a new concept for JL transistors, which would be helpful for the development of poly-Si JL-TFTs and the applications of 3-D integrated circuit and non-volatile memory.

Implementing P-Channel Junctionless Thin-Film Transistor on Poly-Ge0.95Sn0.05 Film Formed by Amorphous GeSn Deposition and Annealing

A systematic investigation on the formation of poly-GeSn film by depositing amorphous GeSn film and subsequent annealing was carried out in this letter to implement high-performance p-channel junctionless thin-film transistors. By using planar devices with the bottom gate structure as the platform, the optimal process condition for forming the poly-GeSn film including annealing temperature, time, and film thickness was determined by X-ray diffraction analysis and device characteristics. It is found that the amorphous GeSn film starts to crystallize at 450 °C and corresponds to better film quality by increasing the temperature to 500 °C. In addition, the film crystallinity is hardly affected as the annealing time exceeds 30 s. With the film thickness in the range between 60 and 12 nm, thinner thickness is beneficial for device operation since it can be turned off more efficiently. Based on the results, then various annealing ambient such as Ar, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O were employed to study its impact on the device performance. Ar-annealed devices exhibit the best performance in terms of the largest drive current capability which is primarily ascribed to the smallest grain boundary density from the largest grain size and the reduced bulk trap density from better defect passivation effect of the dangling bonds in the poly-GeSn film. Even with planar device structure, Ar-annealed devices also demonstrate high ION/IOFF ratio up to 1.7×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> which is due to the good poly-GeSn quality. Moreover, the low-thermal-budget process of 500 °C/30 s paves a new avenue to empower high-performance monolithic 3-D ICs.

Junctionless Thin-Film Transistors Gated by an H₃PO₄-Incorporated Chitosan Proton Conductor.

We fabricated an H3PO4-incorporated chitosan proton conductor film that exhibited the electric double layer effect and showed a high specific capacitance of 4.42 μF/cm2. Transparent indium tin oxide thin-film transistors gated by H3PO4-incorporated chitosan films were fabricated by sputtering through a shadow mask. The operating voltage was as low as 1.2 V because of the high specific capacitance of the H3PO4-incorporated chitosan dielectrics. The junctionless transparent indium tin oxide thin film transistors exhibited good performance, including an estimated current on/off ratio and field-effect mobility of 1.2 × 106 and 6.63 cm2V-1s-1, respectively. These low-voltage thin-film electric-double-layer transistors gated by H3PO4-incorporated chitosan are promising for next generation battery-powered "see-through" portable sensors.

Device Characterization and Design Guideline of Amorphous InGaZnO Junctionless Thin-Film Transistor

Amorphous InGaZnO junctionless thin-film transistors (a-IGZO JL-TFTs) with different active layer thicknesses and thermal treatments were fabricated. The unique feature of a-IGZO JL-TFTs is that all of the active layer and source/drain (S/D) electrodes are realized by the deposition of the InGaZnO thin film. A quantitative analysis to completely deplete the active layer when the device is turned OFF has been performed according to the active layer thickness. The impact of active layer thickness and thermal treatment on the performance of a-IGZO JL-TFTs has been investigated. With the increase in active layer thickness and annealing temperature, the transfer curves shifted to the negative direction. From the effects of S/D series resistance on the performance of a-IGZO JL-TFTs, the series resistance cannot be a serious problem when the contact size is small enough and the active layer is thick enough. To completely deplete the active layer, the impacts of the key device design parameters such as gate oxide thickness, gate workfunction, and high-κ dielectrics on the device performance have been investigated using device simulation.

Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor

In this paper, we report a single grain boundary (GB) junctionless thin film transistor (JLFET) on recrystallized polycrystalline silicon (poly-Si JLFET). Using 2-D simulations, the electrical performance of the poly-Si JLFET is evaluated for different single GB locations in the channel. Without the need for creating the source and the drain regions by implantation, we demonstrate the prospect of achieving thin-film poly-Si JLFETs whose performance is reasonable for silicon film thicknesses less than 10 nm.

Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff

A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (Vbg) has been demonstrated. By applying negative bias of Vbg = −8 V in gate length of 50 nm shows excellent SS (&amp;lt;90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased Ion versus decreased Ioff (ratio &amp;gt; 108), and high Vth modulation. The increased Ion simultaneously decreased Ioff via negative Vbg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with Vbg is a promising for low power circuit, power management, and System-on-Chip applications.

Gate-all-around poly-Si nanowire junctionless thin-film transistors with multiple channels

Polycrystalline silicon (poly-Si) nanowire (NW) junctionless (JL) thin-film transistors composed of gate-all-around (GAA) and multiple channels were demonstrated and characterized. The high surface-to-volume ratio of the NW and a nominal gate length of 0.25 µm lead to a clear improvement in electrical performance, including a steep subthreshold swing (SS; ∼124 mV/decade), a virtual absence of drain-induced barrier lowering (DIBL; 21 ± 13 mV/V), and a high ION/IOFF current ratio (∼1 × 109) under a relatively low voltage condition (VD = 0.3 V, VG = 5 V), resulting from the multiple-channel structure and small grain boundaries and defects under the gate area.

Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate

This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high ION/IOFF current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> ), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> ) of 24 nm is 50 times smaller than conventional JL-TFT with T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.

Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure

This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (>1 μA/μm). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the Ion/Ioff current ratio is over 108 A/A for Lg = 1 μm. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust Vth in multi-Vth circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.

Planar junctionless poly-Si thin-film transistors with single gate and double gate

In this letter, single- and double-gate (SG and DG) planar junctionless (JL) thin-film transistors fabricated via a simple process with an in situ-doped active layer is discussed. The DG structure demonstrated a superior subthreshold swing of 160 mV/dec and a lower off-current of 1.3 × 10−13 A than those of 329 mV/dec and 2.1 × 10−12 A for the SG structure, respectively. It contributes to the enhancement of the gate controllability and ultrathin channel. Consequently, the simple fabrication process of the DG JL device is suitable for future application on system-on-panel and three-dimensional integrated circuits.

High voltage characteristics of junctionless poly-silicon thin film transistors

The breakdown voltage (VBD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state VBD of 53.4 V is several times larger than VBD of 9.5 V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications.

Flexible Transparent Junctionless TFTs With Oxygen-Tuned Indium-Zinc-Oxide Channels

Flexible low-voltage transparent junctionless thin-film transistors (TFTs) with oxygen-tuned indium-zinc-oxide (IZO) active layers are fabricated on polyethylene terephthalate plastic substrates at room temperature with only one shadow mask. IZO films deposited in gradient oxygen ambient are used as the channel and source/drain electrodes without any source/drain junction. High performance with a low subthreshold swing of 0.13 V/decade and a high drain current ON/OFF ratio 106 are obtained in both flat and curving states. A field-effect mobility with a upper limit value of ~60 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V.s is obtained with a gate voltage sweep speed of 0.05 V/s. Such flexible IZO-based junctionless TFTs with lowcost are promising for portable flexible sensor and bioelectronics applications.