Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased Ion versus decreased Ioff

Abstract

A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (Vbg) has been demonstrated. By applying negative bias of Vbg = −8 V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased Ion versus decreased Ioff (ratio > 108), and high Vth modulation. The increased Ion simultaneously decreased Ioff via negative Vbg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with Vbg is a promising for low power circuit, power management, and System-on-Chip applications.