Junctionless Nanowire Research Articles

Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit

In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at the interface of substrate and oxide in the device during the manufacturing due to radiation, stress, process and hot carriers damage which significantly alters various characteristics of the device. The damage due to different profiles of localized charges on several parameters of DG-JNT based P-MOSFET is analyzed. Also, for analog circuit application, this work explicitly reports the comprehensive analysis of localized charge profiles on DG- JNT based CMOS inverter and three Stage Ring Oscillator circuit at 20 nm Gate length. The simulated results are obtained using Silvaco Atlas, TCAD device simulator.

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

The aim of this work is to propose a semi-analytical model for the low frequency noise caused by interface traps in Triple-Gate Junctionless Nanowire Transistors. The proposed model is based on a drain current model, which includes short channel effects influence. The surface potential and the occupied trap density equations are solved self consistently to obtain the traps influence in the static drain current, which is used to determine the trap-related noise. In this work, the low frequency noise of traps in discrete levels is analyzed. The model has been validated with 3D simulations considering different devices characteristics, biases and trap levels. Experimental results have also been used to demonstrate the model suitability.

Junctionless nanowire transistors parameters extraction based on drain current measurements

The aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices.

Temperature-dependent subband mobility characteristics in n-doped silicon junctionless nanowire transistor**Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200503).

We have investigated the temperature-dependent effective mobility characteristics in impurity band and conduction subbands of n-doped silicon junctionless nanowire transistors. It is found that the electron effective mobility of the first subband in 2-fold valleys is higher than that of the second subband in 4-fold valleys. There exists a maximum value for the effective subband mobilities at low temperatures, which is attributed to the increase of thermally activated electrons from the ionized donors in the impurity band. The experimental results indicate that the effective subband mobility is temperature-dependent on the electron interactions by thermal activation, impurity scattering, and intersubband scattering.

Detection of ultra-low protein concentrations with the simplest possible field effect transistor

Silicon nanowire (Si NW) sensors have attracted great attention due to their ability to provide fast, low-cost, label-free, real-time detection of chemical and biological species. Usually configured as field effect transistors (FETs), they have already demonstrated remarkable sensitivity with high selectivity (through appropriate functionalisation) towards a large number of analytes in both liquid and gas phases. Despite these excellent results, Si NW FET sensors have not yet been successfully employed to detect single molecules of either a chemical or biological target species. Here we show that sensors based on silicon junctionless nanowire transistors (JNTs), the simplest possible transistors, are capable of detecting the protein streptavidin at a concentration as low as 580 zM closely approaching the single molecule level. This ultrahigh detection sensitivity is due to the intrinsic advantages of junctionless devices over conventional FETs. Apart from their superior functionality, JNTs are much easier to fabricate by standard microelectronic processes than transistors containing p–n junctions. The ability of JNT sensors to detect ultra-low concentrations (in the zeptomolar range) of target species, and their potential for low-cost mass production, will permit their deployment in numerous environments, including life sciences, biotechnology, medicine, pharmacology, product safety, environmental monitoring and security.

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

This paper presents the extension of proposed physically-based continuous compact analytical model of triple gate junctionless nanowire transistors for accurate description of device electrical characteristics in a wide temperature range from room temperature up to 500 K. The model validation is performed by comparison against tridimensional numerical simulation and experimental data showing very good agreement, with continuous description of drain current and its derivatives in all regions of operation and temperatures.

Demonstration of Thermally-Assisted Programming With High Speed and Improved Reliability for Junctionless Nanowire NOR Flash Memory

This study demonstrated the thermally-assisted (TA) programming of a NOR flash memory device, which was composed of a junctionless silicon nanowire with gate-all-around structure. Fast programming was achieved with the aid of Joule heat, which was generated in a homogeneously heavily doped SiNW by a voltage difference between the source and drain. Its programming speed is the fastest among various NOR flash memories ever reported. The mechanism for programming NOR flash memory inevitably degrades the quality of the tunneling oxide. But the proposed thermally-assisted programming provides simultaneous curing of the damaged tunneling oxide.

Threshold Voltage Characteristics for Silicon Nanowire Field-Effect Transistor With a Double-Layer Gate Structure

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells.

Fully Analytical Compact Model for the I–V Characteristics of Large Radius Junctionless Nanowire FETs

In this paper, we developed an analytical model for the $I{-}V$ characteristics of junctionless nanowire FETs (JLNWFETs) in which the radius of the nanowire is large enough to allow quantum confinement effects to be neglected. The model is valid for all bias regimes, subthreshold, depletion and accumulation, and it is fully analytical, do not requiring the numerical solution of integrals or transcendental equations. Our compact model is validated in comparison to available results in the literature, with agreement equivalent to much more complex approaches.

Drain Conductance Oscillations in Poly-Si Junctionless Nanowire Thin-Film Transistors

The drain conductance oscillations are simultaneously observed in the trigated and double-gated poly-Si junctionless (JL) nanowire thin-film transistors (TFTs). The strongest oscillations appear at ${V} _{\text {GS}}$ of 1 V and $V_{\text {DS}}$ of 4–5 V/6–7 V in 0.35- $\mu \text{m}$ /5- $\mu \text{m}$ poly-Si JL nanowire TFTs. To explain the drain conductance oscillations, in addition to the separated sub-bands and Coulomb blockade effect, the space-charge-potential barrier/grain boundary (GB) potential barrier in the channel and the kink effect in the output characteristics should be considered. The space-charge-potential barrier is affected by the unstable trapped electrons at GB and leads to the drain conductance oscillations. Due to the kink effect, an anomalous increase of the current in the output characteristics can enhance the conductance oscillations. Moreover, the channel of the double-gated device shows higher degree of crystallinity by solid-phase crystallization. Compared with the trigated device without solid-phase crystallization, less GB potential barriers in the channel of the double-gated device lead to a higher mobility in the channel, and these electrons can easily destroy the stability of the trapped electrons at the GBs, resulting in the stronger drain conductance oscillations. Therefore, the physical mechanisms are proposed to understand the drain conductance oscillations well in poly-Si JL nanowire TFTs.

Mobility Calculation of Ge Nanowire Junctionless and Inversion-Mode Nanowire NFETs With Size and Shape Dependence

The electron mobility in junctionless (JL) and inversion-mode (IM) Ge nanowire nFETs with [110] channel direction is studied by theoretical calculations. Channels with different widths and cross-sectional shapes are compared. The mobility calculation is based on the Kubo–Greenwood formulation for 1-D systems. Phonon scattering, Coulomb scattering (CS), and surface roughness scattering (SRS) are considered. With the equivalent oxide thickness of 1 nm, diamond and square channels have the higher mobility than circular channels at low channel carrier density, but the lower mobility at high channel carrier density for both JL and IM channels. This mobility trend is explained by the SRS on the sharp corners in diamond and square channels. The JL channels have the lower mobility than IM channels at low channel carrier density due to additional CS. At high channel carrier density, SRS dominates, and the JL channel has the slightly higher mobility than the IM channel due to its weaker SRS. The mobility difference between JL and IM is negligible for 5-nm narrow wires.

Accuracy balancing for the simulation of gate-all-around junctionless nanowire transistors using discrete Wigner transport equation

We report the application of the discrete Wigner transport equation to the simulation of gate-all-around junctionless nanowire transistors (JLNWTs). We show that unphysical simulation results are obtained unless we pay attention to the accuracy balancing problem. An empirical criterion based on the subthreshold swing of the JLNWT is proposed for the accuracy balancing. Using this criterion, we investigate the characteristics of JLNWTs with the quantum effect fully considered.

Enhancement-Mode Recessed Gate and Cascode Gate Junctionless Nanowire With Low-Leakage and High-Drive Current

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., $1\times 10^{20}$ cm−3) for large on-state current ( $I_{ON} $ ) and low contact resistance, it becomes depletion mode ( ${V}_{\textsf {TH}} V for nMOS and ${V}_{\textsf {TH}} > 0$ V for pMOS). In order to have enhancement-mode device ( ${V}_{\textsf {TH}} > 0$ V for nMOS and ${V}_{\textsf {TH}} V for pMOS), low doping (e.g., 1019 cm−3)is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., $1.5 \times 10^{20}$ cm−3). The proposed concepts are validated by TCAD simulations using classical and quantum (nonequilibrium Green’s function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . The second one is to have a cascode-/dual-gate structure which can further enhance ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , reduce ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and increase ${V}_{\textsf {TH}}$ with equivalent on-state gate length ( ${L}_{G}) = 5$ nm and off-state ${L}_{G} = 10$ nm and $50\times $ increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio. Such ideas are applicable to other JL devices such as FinFET, SOI, and nanosheets.

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETs.

The analog figure-of-merits (FOMs) of conventional inversion-mode (IM) and junctionless (JL) NanoWire Field Effect Transistor (NWFET) have been investigated, considering the gate Work-Function Variability (WFV) and Random Discrete Dopant (RDD) using 3-dimensional (3D) TCAD simulation. While the JL-NWFET shows higher immune to WFV on analog FOMs, it can be easily affected by RDD due to higher channel doping level. On the other hand, the IM-NWFET shows stronger correlation between transconductance (gm) and gate capacitance (Cgg), leading to similar variation in cut-off frequency (ft) even though it shows larger gm and Cgg variation compared to JL-NWFET.

Transport spectroscopy through dopant atom array in silicon junctionless nanowire transistors**Project supported by the National Key R&D Program of China (Grant No. 2016YFA0200503) and the National Natural Science Foundation of China (Grant No. 61327813).

We demonstrate electron transport spectroscopy through a dopant atom array in n-doped silicon junctionless nanowire transistors within a temperature range from 6 K to 250 K. Several current steps are observed at the initial stage of the transfer curves below 75 K, which result from the electron transport from Hubbard bands to one-dimensional conduction band. The current-off voltages in the transfer curves have a strikingly positive shift below 20 K and a negative shift above 20 K due to the electrostatic screening induced by the ionized dopant atoms. There exists the minimum electron mobility at a critical temperature of 20 K, resulting from the interplay between thermal activation and impurity scattering. Furthermore, electron transport behaviors change from hopping conductance to thermal activation conductance at the temperature of 30 K.

Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire Transistors

This work evaluates, for the first time, the roles of the intrinsic capacitances and the series resistance on the dynamic response of p- and n-type Junctionless Nanowire Transistors. The dynamic behavior evaluation will be carried out through the analysis of the limitation imposed by such parameters on the maximum oscillation frequency (fmax). In the sequence, it will be shown the impacts of fmax and the carriers’ transit time on the minimum switching time presented by JNTs. It has been observed that Junctionless devices present lower fmax than inversion mode transistors of similar dimensions due to higher resistance and lower transconductance. However, the intrinsic capacitances of such devices are smaller than the inversion mode ones, which compensates part of the degradation on fmax caused by the other parameters. Besides that, it is shown that transit time can be important on the dynamic behavior of long devices, but plays a negligible role in shorter ones.

Junctionless Tunneling Nanowire for Steep Subthreshold Slope

Using standardized simulations, we report a meticulous learning of the Junctionless nanowire with tunneling mechanism and the dependence of Subthreshold slope on operational parameters by varying the channel diameter, Gate length and doping concentration using Synopsys Sentaurus TCAD simulations. For the first time, Junctionless Nanowire in the company of tunneling architecture is proposed and explored. Our simulation study shows that a decrease in channel diameter and doping concentration results in higher band to band generation and steeper slope. Junctionless tunneling nanowire of diameter 10 nm, gate length of 20 nm, and uniform doping concentration of 1e19 cm−3 obtains steepest Subthreshold swing of about 8 mV/dec (point) and 52 mV/dec (average), an on/off current ratio of 1010, on current of 10−5 A/um.

Improving electrical performance in Ge–Si core–shell nanowire transistor with a new stripped structure

A new device structure based on Ge–Si core–shell nanowire is proposed. Owing to the fact that the Si shell is stripped at the source/drain end, the density and electrostatic potential of the holes is gradually distributed in the source/drain region of the new structure, which results in a higher gradient of quasi-Fermi potential in the channel underneath the gate. We observe a higher current ratio for the on-off state and improved output characteristics in the new structure via TCAD simulation. Besides, in the proposed structure we can adjust the on-state current by changing the source/drain length for the same gate length. This provides a feasible approach to optimizing a junctionless nanowire transistor device.

Influence of dopant concentration on electrical quantum transport behaviors in junctionless nanowire transistors**Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200503), the Program for Innovative Research Team (in Science and Technology) in University of Henan Province, China (Grant No. 18IRTSTHN016), and the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126).

We discuss the random dopant effects in long channel junctionless transistor associated with quantum confinement effects. The electrical measurement reveals the threshold voltage variability induced by the random dopant fluctuation. Quantum transport features in Hubbard systems are observed in heavily phosphorus-doped channel. We investigate the single electron transfer via donor-induced quantum dots in junctionless nanowire transistors with heavily phosphorus-doped channel, due to the formation of impurity Hubbard bands. While in the lightly doped devices, one-dimensional quantum transport is only observed at low temperature. In this sense, phonon-assisted resonant-tunneling is suppressed due to misaligned levels formed in a few isolated quantum dots at cryogenic temperature. We observe the Anderson-Mott transition from isolate electron state to impurity bands as the doping concentration is increased.

Static and dynamic compact analytical model for junctionless nanowire transistors

This paper presents a compact analytical model for the static and dynamic electrical characteristics of Junctionless Nanowire Transistors. The static drain current model formulation is derived from the 2D solution of the Poisson equation with appropriate boundary conditions and long-channel devices, leading to a continuous effective surface potential that accounts for the conduction in partial depletion and accumulation regimes. The long-channel model is modified to account for short-channel effects by using the coupled solution of 3D Laplace equation with the 2D Poisson equation. The substrate bias influence on the drain current is also included in the model formulation. The charges at the device terminals are differentiated with respect to the applied biases leading to an analytical description of the transconductances and transcapacitances. The proposed model is validated using experimental data at different bias conditions and temperatures, showing very good agreement.