Enhancement-Mode Recessed Gate and Cascode Gate Junctionless Nanowire With Low-Leakage and High-Drive Current

Abstract

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., $1\times 10^{20}$ cm−3) for large on-state current ( $I_{ON} $ ) and low contact resistance, it becomes depletion mode ( ${V}_{\textsf {TH}} V for nMOS and ${V}_{\textsf {TH}} > 0$ V for pMOS). In order to have enhancement-mode device ( ${V}_{\textsf {TH}} > 0$ V for nMOS and ${V}_{\textsf {TH}} V for pMOS), low doping (e.g., 1019 cm−3)is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., $1.5 \times 10^{20}$ cm−3). The proposed concepts are validated by TCAD simulations using classical and quantum (nonequilibrium Green’s function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . The second one is to have a cascode-/dual-gate structure which can further enhance ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , reduce ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ and increase ${V}_{\textsf {TH}}$ with equivalent on-state gate length ( ${L}_{G}) = 5$ nm and off-state ${L}_{G} = 10$ nm and $50\times $ increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio. Such ideas are applicable to other JL devices such as FinFET, SOI, and nanosheets.