Junctionless Nanowire Research Articles

Retracted] Effects of Novel Material Field Effect Transistor for Heterogeneous Energy and Traffic‐Aware Secure Applications

The advent of the automated technological revolution has enabled the Internet of Things to rejuvenate, revolutionize, and redeem the services of sensors. The recent development of microsensor devices is distributed in a real‐world terrestrial environment to sense various environmental changes. The energy consumption of the remotely deployed microsystems depends on its utilization efficiency. Improper utilization of sensor nodes’ heterogeneity could lead to uneven energy consumption and load imbalance across the network, which will degrade the performance of the network. The proposed heterogeneous energy and traffic aware (HETA) considers the key parameters such as delay, throughput, traffic load, energy consumption, and life span. The residual energy and a minimum distance between the base station and cluster members are taken into consideration for the cluster head selection. The probability of hitting data traffic has been utilized to analyse energy and traffic towards the base station. The role of the sensor node has been realized and priority‐based data forwarding are also proposed. As a result, the heterogeneous energy and traffic aware perform well in balancing traffic towards the base station, which is analysed in terms of maximum throughput and increase in a lifetime of heterogeneous energy networks more than 5000 rounds, and the algorithm outperforms 34.5% of nodes are alive with transmissible energy. The proposed research also endorses unequal clustering and minimum energy consumption. We have modeled our proposed research using various p‐type junctionless nanowire FET without doping injunctions. The materials used in this analysis were silicon (Si), germanium (Ge), indium phosphide (InP), gallium arsenide (GaAs), and Al(x)Ga(1−x)As. The dimensions of the p‐type cylindrical nanowire channel were 25 nm long and 10 nm in diameter.

On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier.

Linearity performance analysis of junctionless nanotube tunnel field effect transistor

The article provides linearity performance parameter of junctionless nanotube TFET (JL-NT-TFET) for the application of ultra-low standby power and radio frequency ICs (RFICs). The proposed charge plasma device uses an inner gate with a similar workfunction as the outer gate electrode. The inner gate of the device provides better electrostatic controllability, increases turn-on capability. JL-NT-TFET shows the subthreshold swing of 20.5 mV decade, minimum leakage current, and higher current as compared to junctionless nanowire TFET (JL-NW-TFET). Linearity performance analyzed in terms of VIP2, VIP3, IIP3 and 1-dB compression point. Results obtained from JL-NTTFET is further compared to JL-NW-TFET. Simulation results of both the devices indicate that the JL-NT-TFET shows better linearity performance, hence it can be applied to low power high-frequency applications.

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures

This work studies the effects of the temperature variation, from 300K to 500K, on the electrical parameters of SOI n-type and p-type junctionless nanowire transistors. The temperature influence on the threshold voltage, subthreshold slope, and the effective carrier mobility were analyzed. The mobility scattering mechanisms were analyzed and show that nanowire devices have the phonon scattering as their major component, although there is a significant component of the ionized impurity scattering that can be identified as well. These electrical parameters were also analyzed for short channel devices with a channel length of 40nm. P-type devices showed higher degradation with the temperature as the doping concentration is higher than n-type devices.

Analysis of Junctionless Nanowire Transistor with Heterojunction, Metal Nitride and Dual Metal Gate

Analysis of Junctionless Nanowire Transistor with Heterojunction, Metal Nitride and Dual Metal Gate

The Roles of the Gate Bias, Doping Concentration, Temperature and Geometry on the Harmonic Distortion of Junctionless Nanowire Transistors Operating in the Linear Regime

The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and the geometry on the overall linearity have been evaluated. The increase of the series resistance associated both to the variation of the physical parameters and the incomplete ionization effect has shown to improve the second order distortion and degrade the third order one.

Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors

Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented. The model is validated using tridimensional numerical simulations.

Impact of the Series Resistance in the I-V Characteristics of Junctionless Nanowire Transistors and its dependence on the Temperature

The effect of the source/drain parasitic resistance (RS) on the I-V characteristics of Junctionless Nanowire Transistors (JNTs) has been evaluated through experimental and simulated data. The impact of several parameters such as the temperature, the fin width, the total doping concentration, the source/drain length and the source/drain doping concentration on RS has been addressed. The source/drain parasitic resistance presented by JNTs was compared to the one presented by classical inversion mode (IM) triple gate devices, showing opposite behavior with the temperature variation in IM triple transistors and JNTs. In the latter, a reduction on RS is noted with the temperature increase, which is related to the incomplete ionization. This effect inhibits the presence of a Zero Temperature Coefficient (ZTC) operation bias in the Junctionless devices.

Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion

This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature range of 223 K up to 473 K. The non-linearity or harmonic distortion (HD) has been evaluated in terms of the total and the third order distortions (THD and HD3, respectively) at a fixed input bias and at a targeted output swing. Several parameters important for the HD evaluation have also been observed such as the transconductance to the drain current ratio (gm/IDS), the Early voltage (VEA) and the intrinsic voltage gain (AV). Trigate devices showed maximum AV around room temperature whereas in JNTs the intrinsic voltage gain increases with the temperature. Due to the different AV characteristics, Junctionless transistors present improved HD at higher temperatures whereas inversion mode Trigate devices show better HD properties at room temperature.When both devices are compared, Junctionless transistors present better THD and HD3 with respect to the IM Trigate devices.

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the S i 1 − x G e x virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the S i 1 − x G e x virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band-to-band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator.

Design and optimization of junctionless-based devices with noise reduction for ultra-high frequency applications

This paper offers the study of the noise performance of four devices namely junctionless dual-gate FET (JL-DGFET), junctionless nanowire FET (JL-NWFET), charge-plasma based dopingless dual-gate FET (DL-DGFET) and dopingless nanowire FET (DL-NWFET). This work examines the maximum Noise-Figure (NFmax.), Auto-correlation factor ( )/( ), cross-correlation factor ( ), and output impedance (real Zo). To understand the performance of devices, analog characteristics of all four devices and effect on these characteristics with the variations of different device structure parameters are analyzed and compared. Internal physics of device is understood by device design parameters such as electric field, channel potential, carrier mobility and carrier concentration. It is observed from the simulated results that JL-DGFET has better noise performance, highest ION/IOFF current ratio than other devices.

Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications

Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher Ids, gm, gd and fT compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing ION/IOFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (Rch), advanced early voltage (VEA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S21 and S12) and reflection coefficients (S11 and S22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs.

Room temperature terahertz detector based on single silicon nanowire junctionless transistor with high detectivity

In this work, the n-type single silicon nanowire (NW) based junctionless field-effect transistor (FET) is demonstrated as an efficient terahertz (THz) detector. For the effective coupling of the THz radiations with NW junctionless FET, the lobes of the rounded bow-tie antenna are connected to the gate and source terminals of the device. The antenna design is optimized with proper impedance matching conditions to achieve maximum power transfer between antenna and detector. The simulated antenna resonates at 0.43 THz frequency with 19 GHz bandwidth. Further simulations have been done on Lumerical finite difference time domain software to analyze the electric field distribution profile. To investigate the optical response of this optimized antenna design, an array of the simulated antenna has been fabricated and its transmission spectra are measured. Finally, the simulated antenna has been integrated with the n-type NW junctionless transistor. A maximum responsivity of 468 V W−1 at 0.425 THz frequency and noise-equivalent-power of ∼ 10−9W/Hz1/2 is obtained at room temperature. The complementary metal-oxide-semiconductor’s compatibility, ease of integration on chips, possibility to realize multiple pixel arrays, andscalability to higher frequencies, make this device promising for THz electronics.

Ultrahigh-Density 3-D Vertical RRAM With Stacked Junctionless Nanowires for In-Memory-Computing Applications

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors

Effects of Work-function Variation on Performance of Junctionless and Inversion-mode Dual-metal Gate Nanowire Transistors

Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires

This work presents a study on the effects of single interface traps throughout the Junctionless Nanowire Transistor (JNT). The results are obtained by analyzing the Random Telegraph Signal noise of the device, which consists of an exception of the generation-recombination noise. The results obtained are mostly from numerical simulation, validated through experimental data. As in physical devices, it is impossible to obtain a single trap in specific locations, we have used a distribution of traps with similar characteristics in a way that they behave like a single trap. The results show the behave considering a set of traps distributions, using an exponential model. The traps are distributed from the conduction band to the valence band.
 Keywords– JNT; RTS Noise; G-r Noise; Interface Traps.

Surface Potential-Based Analytical Modeling of Electrostatic and Transport Phenomena of GaN Nanowire Junctionless MOSFET

This article presents a comprehensive analytical investigation of electrostatic and transport phenomena of GaN nanowire (NW) junctionless (JL) MOSFET. The evolution of the proposed model involves the solution of quasi 2-D Poisson equation with appropriate boundary conditions to obtain effective surface potential as a function of gate voltage. The mobile carrier density derived from the surface potential model is used to formulate the core transport model as well as to analyze the electrostatic characteristics for various physical device parameters. Short channel effect and certain nonideal effects including velocity saturation, mobility degradation, and channel length modulation have been incorporated in the core transport model. The impact of physical device parameters including channel length, NW radius, and oxide thickness on the performance metrics of the device such as subthreshold slope (SS), drain-induced barrier lowering (DIBL), and threshold voltage has been rigorously investigated. Upon analyzing the transport properties of the device, steep SS of 68 mV/dec, DIBL of 27 mV/V, and switching figure of merit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${Q}$ </tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$= {g}_{m}/\text {SS}$ </tex-math></inline-formula> ) of 0.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$({\mu }\text {S}/{\mu }\text {m})/(\text {mV}/\text {dec})$ </tex-math></inline-formula> have been attained which makes the GaN NW JL MOSFET a promising candidate for emerging low-power application. The results of this work exhibit very good agreement with 3-D TCAD simulation and reported experimental results and thereby enhancing the reliability of the proposed model.

Correlation between the NBTI Effect and the Surface Potential and Density of Interface Traps in Junctionless Nanowire Transistors

This paper discusses the nature of degradation by NBTI effect in MOS junctionless devices when varying the density of interface traps and surface potential. The data obtained in simulations are compared with results from physical devices and it is demonstrated how the quality of gate oxide affects the performance of such transistors, when the density of traps, the channel width, the doping concentration and the gate bias are varied.

Impact of asymmetrical source/drain offsets on the operation of dual-gated poly-Si junctionless nanowire transistors

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

A 2-D compact DC model for engineered nanowire JAM-MOSFETs valid for all operating regimes

This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate nanowire junctionless accumulation mode MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device.