Junctionless Nanowire Research Articles

(Digital Presentation) Comparison of Width and Temperature Influence on DIBL Effect in Junctionless and Inversion Mode Nanowire MOSFETs

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.

(Invited) Strategies for Characterization and Parameter Extraction of Vertical Junction-Less Nanowire FETs Dedicated to Design Technology Co-Optimization

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

Physics based analytical modeling and simulation of Cylindrical Junctionless Nanowire Ferroelectric field effect transistor (CJNFe-FET) for enhanced analog performance

Physics based analytical modeling and simulation of Cylindrical Junctionless Nanowire Ferroelectric field effect transistor (CJNFe-FET) for enhanced analog performance

Design and simulation of junctionless nanowire tunnel field effect transistor for highly sensitive biosensor

This paper investigates symmetrical design of a Junctionless Nanowire Tunnel-Field-Effect-Transistor (JL-NWTFET) for highly sensitive biosensor. JL-NWTFET deployed using Gate-All-Around (GAA) structure and Dielectric-Modulation (DM) technique to detects the bio-logical molecules such as uricase, streptavidin, protein, biotin, uriease, Amino-propyl triethoxysilane (APTS), ChOx etc. The variation in the drain current (ID), subthreshold slope (SS), transconductance (gm), and ION/IOFF ratio considered as the sensitivity parameters of the JL-NWTFET to detect different biological molecules in the cavity area. The cavity area is formed by a layer in between the source-gate oxides and source-gate electrodes. The JL-NWTFET shows the reduced leakage currents in terms of Short-Channel-Effects (SCEs) and superior controllability over the channel. The proposed JL-NWTFET has been designed with uniform doping concentration (1 × 10−19 cm−3), and gate work-function (φgate = 4.8eV). The high sensitivity (∼109) is observed for APTS biomolecule with dielectric constant (K = 3.57).

Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain

We present, in this paper, optimized nanotube (NT) and nanowire (NW) junctionless field-effect transistor (JLFET) architectures of gate-induced drain leakage (GIDL). At the source/ drain–channel interface, SiGe creates a valence energy band discontinuity which alleviates lateral band-to-band tunneling (L-BTBT) of electrons in the OFF-state. It is established through 2-D TCAD simulations that inclusion of SiGe decreases L-BTBT in the NTJLFET by >5 orders, thus leading to a substantial ION/IOFF of with precision 1012 for a 20 nm gate length which is not attainable in the conventional NTJLFET (ION/IOFF ∼ 106). Furthermore, degraded OFF-state current in NWJLFET because of conventional charge-sharing effect improves with the inclusion of SiGe by ∼2 orders of magnitude. Additionally, it is effective to place SiGe layers positioned at the source and drain regions and SiGe/ Si interface inside or at the channel region. Based on the proposed design guidelines, we show that the optimized SiGe S/D NTJLFET is effective in reduction of L-BTBT GIDL when gate length is scaled to 5 nm.

Impact of Negative Capacitance Junctionless Nanowire (NCJLNW) MOSFET on Ring Oscillator Design and Analysis

This work presents the analysis of NCJLNW for low power analog/RF applications; this device shows reduced power consumption, reduced SCEs, smaller leakage and higher Ion/Ioff ratio. The results indicate that the proposed device improves the intrinsic gain, cut-off frequency, transconductance and reduces DIBL. The analysis of band-energy, surface-potential and electric-field has also shown promising results. Ring oscillator has been designed using this device; the analysis of the oscillator presents lower voltage of operation resulting into reduced power consumption, and high noise immunity. The frequency of oscillation is found to be higher at 172.1 GHz at a channel length of 20 nm.

Sensitivity Analysis of Nanowire FET Biosensor

A nanowire junctionless FET biosensor has been modelled with COMSOL Multiphysics. The high sensitivity of the device in depletion regime was observed. The sensitivity dependence on variations of species concentration in analyte surrounding the nanowire has been studied. It has been demonstrated that the thinner is the nanowire, the higher is the sensitivity and even a single molecule affects the drain current. The model is useful for sensor optimization.

Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement

In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is confirmed from deep depletion to accumulation and from linear to saturation, based on the numerical solution of the Schrödinger equation using Technology Computer Aided Design (TCAD) simulations. This represents an important stage toward AC small signal analysis of junctionless nanowire-based circuits.

Thermal Conductivity Model to Analyze the Thermal Implications in Nanowire FETs

In this article, a thermal conductivity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) model is proposed (i.e., dependent on the temperature, thickness, and doping concentration) for investigating the thermal behavior of silicon-on-insulator (SOI)-based devices. The proposed model is less complex in calculating the thermal conductivity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) compared to the existing model because the analysis of the existing model is complicated due to multiple equations. The proposed model is also easier to implement in the TCAD simulator than the existing model, which is currently being used in the Sentaurus TCAD electrothermal module to study the thermal behavior of the devices. The thermal conductivity ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> ) predictions are analyzed using the proposed model, which agrees with the reported experimental data and existing complex analytical models. The thermal behavior of junctionless nanowire (JL-NW) FET is investigated using the sub-5-nm technology node-based physical parameters. It is observed that the thermal behavior depends on the temperature, thickness, and doping concentrations of the SOI devices. The proposed model provides an insightful and accurate analysis of the behavior of the SOI-based nanodimension transistors.

Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation.

Optimization of inversion mode and junctionless nanowire MOSFET for improved sensitivity to process induced variability

Optimization of inversion mode and junctionless nanowire MOSFET for improved sensitivity to process induced variability

Effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistor

We investigated the effect of charge trapping on electrical characteristics of silicon junctionless nanowire transistors which are fabricated on heavily n-type doped silicon-on-insulator substrate. The obvious random telegraph noise and current hysteresis observed at the temperature of 10 K indicate the existence of acceptor-like traps. The position depth of the traps in the oxide from Si/SiO2 interface is 0.35 nm, calculated by utilizing the dependence of the capture and emission time on the gate voltage. Moreover, by constructing a three-dimensional model of tri-gate device structure in COMSOL Multiphysics simulation software, we achieved the trap density of 1.9 × 1012 cm–2 and the energy level position of traps at 0.18 eV below the intrinsic Fermi level.

Interface traps density extraction through transient measurements in junctionless transistors

This paper presents an extraction method for the interface traps density on Junctionless Transistors (JNTs) using an adapted charge pumping technique. To the best of our knowledge, this is the first work to apply this method in JNTs. Initially, it was stated through numerical simulations that a transient current, which increases with the trap density, is observed in the devices when the charge pumping method is applied. Then, a measurement setup was proposed to extract the pumping current resultant from a gate pulse and a mathematical expression was proposed to extract the density of trapped charges in the Oxide/Silicon interface (Nit). Aiming to demonstrate the method applicability for determining the JNTs interface quality, it was applied to simulations considering different trap densities as well as to experimental data of Junctionless Nanowire Transistors. It was observed that the method accuracy increases for larger trap densities and presents agreement to theoretical data for Nit > 1 × 1011 cm−2.

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET Implemented in Verilog-A for Circuit Simulation

Analytical Compact Model of Nanowire Junctionless Gate-All-Around MOSFET Implemented in Verilog-A for Circuit Simulation

A unified 2-D model for nanowire junctionless accumulation and inversion mode MOSFET in quasi-ballistic regime

A unified 2-D continuous potential model for cylindrical nanowire junctionless accumulation mode (JAM) MOSFET and conventional inversion mode (IM) MOSFET has been presented in this manuscript. The 2-D Poisson’s equation in cylindrical coordinates is solved analytically with the help of the superposition principle and evanescent mode analysis of the Fourier-Bessel series is performed. Both free and depletion charges are considered in the 2-D Poisson’s equation. The model thus derived is continuous across different operation regimes (depletion and accumulation/inversion) with respect to VGS. Further, a threshold voltage model is also derived from the potential model and an expression of drain-induced barrier lowering (DIBL) is formulated. The short channel drain current model is derived from the potential-based charge model and quasi-ballistic transport velocity model. Furthermore, models for transconductance (gm) and output conductance (gd) is also formulated from the drain current model. A 3-D TCAD tool from CogendaTM has been used to numerically verify our proposed unified analytical model.

Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

Physical analysis of β-Ga2O3 gate-all-around nanowire junctionless transistors: short-channel effects and temperature dependence

VERILOG_A IMPLEMENTATION OF NANOWIRE JUNCTIONLESS ISFET COMPACT MODEL AND READ-OUT CIRCUIT DESIGN

In this paper, we implement nanowire (NW) junctionless (JL) ISFET model in Verilog-A hardware language. The Verilog-A implementation would allow the NW ISFET integration with signal processing circuits. The simulated by the code pH values are compared with the corresponding data from COMSOL simulations, and a good agreement is observed. The readout circuit based on amperometric switched- capacitors schemes is designed. The readout circuit has introduced good linearity in pH values range from 3 to 7.

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

This paper proposes hafnium (IV) oxide (HfO2) as gate oxide material of the nanowire junctionless transistor (NJT) to replace the conventional silicon dioxide (SiO2). Leakage current usually increased due to an increase of tunneling of electronsin SiO2transistor when the thickness oxide (tox) of the gate material is below 2nm. The main advantages of HfO2is high dielectric constant k of 20 to 25 which is almost 6 times than that of SiO2. Similarly, HfO2has an energy band gap of 5.3 to 5.7eV. As a result, low leakage current and short channel effects (SCEs) was experienced. An increased in the gate capacitance of the device leads to improve the performance of the device without affecting the enhanced leakage current. All these was achieved by designing and simulating the device using the SDE tools of Sentaurus TCAD. Electrical characteristics was extracted using the Sdevice tools of the software. The performance was significantly increased to approximately 1010using HfO2material

Fabrication of junction-free Cu nanowire networks via Ru-catalyzed electroless deposition and their application to transparent conducting electrodes

Over the past few years, metal nanowire networks have attracted attention as an alternative to transparent conducting oxide materials such as indium tin oxide for transparent conducting electrode applications. Recently, electrodeposition of metal on nanoscale template is widely used for formation of metal network. In the present work, junctionless Cu nanowire networks were simply fabricated on a substrate by forming a nanostructured Ru with 80 nm width as a seed layer, followed by direct electroless deposition of Cu. By controlling the density of Ru nanowires or the electroless deposition time, we readily achieve desired transmittance and sheet resistance values ranging from ∼1 kΩ sq−1 at 99% to 9 Ω sq−1 at 89%. After being transferred to flexible substrates, the nanowire networks exhibited no obvious increase in resistance during 8000 cycles of a bending test to a radius of 2.5 mm. The durability was verified by evaluation of its heating performance. The maximum temperature was greater than 180 °C at 3 V and remained constant after three repeated cycles and for 10 min. Transmission electron microscopy and x-ray diffraction studies revealed that the adhesion between the electrolessly deposited Cu and the seed Ru nanowires strongly influenced the durability of the core–shell structured nanowire-based heaters.

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band into the channel valence band during the OFF-state. Impact of varying WF at channel–drain junction on the device characteristics is studied. It is observed that SBH \(\leqslant 0\) eV is required to mitigate L-BTBT compared to the conventionally doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and is termed as the lateral SB tunneling (L-SBT). In contrast with JL NW FET, the process variation immunity (varying channel doping, \({N}_{\mathrm{Ch}}\) and NW diameter, \({d}_{\mathrm{NW}}\)) and the ON-state current of the proposed device are not compromised at the expense of lower OFF-state L-SBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ± 20% change in \({N}_{\mathrm{Ch}}\), \(\Delta {I}_{\mathrm{OFF}}\)/\({I}_{\mathrm{OFF}}\) of 7% compared to 97% in NW JL FET is observed.