Junctionless Gate-all-around Research Articles

Junctionless Versus Inversion-Mode Gate-All-Around Nanowire Transistors From a Low-Frequency Noise Perspective

The low-frequency noise behavior of junctionless (JL) gate-all-around (GAA) nanowire (NW) FETs has been investigated and compared with similar inversion-mode (IM) devices. It is shown that the predominant 1/f-like noise is governed by carrier number fluctuation (CNF) around threshold voltage operation, while for the p-channel transistors, a pronounced increase in the noise power spectral density is observed at higher gate voltage overdrives. This is due to the impact of the access region to the flicker noise. While the CNF noise is roughly one decade higher for the n-channel than for the p-channel transistors, the opposite holds for the access-related component for both IM and JL GAA NWFETs. It is, finally, observed that the CNF noise is on the average slightly lower in the JL devices compared with their IM counterparts; the origin of this trend will be discussed.

SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices

The SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2 and Si3N4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.

ANFIS-based Approach to Predict the Degradation-related Ageing of Junctionless GAA MOSFET

The estimation of average lifetime has been considered as a serious reliability concern for VLSI components. However, with the tremendous downscaling of MOSFET devices, it becomes very difficult to predict such measure with satisfactory precision due to the amplified parasitic effects at the deep scale level. The present work aims at investigating the efficiency of adaptive neuro-fuzzy inference system approach as a predictor of junctionless gate all around MOSFET device lifetime. Our predictions are compared versus the numerical results obtained by ATLAS simulator, where a good agreement is obtained.

A compact explicit DC model for short channel Gate-All-Around junctionless MOSFETs

In this paper we provide solutions to update a long channel model in order to take into account the short channel effects. The presented model is for the junctionless GAA MOSFETs. The resulting model is analytical, explicit and valid for depletion and accumulation regimes, and consists of simple physically based equations, for better understanding of this device, and also easier implementation and better computation speed as a compact model. The agreement with TCAD simulations is very good.

Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I on/I off ratio directing improved digital performance at higher channel lengths, reduced channel resistance (R ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage (V EA) which shows the capability for high-gain amplification and higher g m/g d directing high intrinsic dc gain. Higher f Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g m3. Reduction in g m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

Band-to-Band Hot Hole Erase Mechanism of p-Channel Junctionless Silicon Nanowire Nonvolatile Memory

In this paper, p-channel junctionless (JL) silicon-oxide–nitride-oxide–silicon (SONOS)-type nonvolatile memory (NVM) devices with gate-all-around (GAA) nanowire (NW) structure by using silicon-nanocrystal for the charge-trapping layer are presented. The devices exhibited good erase efficiency and excellent retention behavior and can be used in system-on-panel and 3-D-stacked flash memory applications. In addition, a band-to-band hot hole (BBHH) method for erasing is proposed and compared with the Fowler–Nordheim (FN) tunneling method. Because FN erasing requires a high gate voltage, BBHH erasing, which requires a low voltage, can increase the service life of the memory. Channel hot electron and band-to-band hot electron were used for programming and yielded low programming efficiency for the p-channel JL GAA NW NVM devices because of a lack of electron carriers. The program/erase efficiency is related to the channel type in JL NVM devices.

Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor.

Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 μA/μm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.

Improved analog and RF performances of gate-all-around junctionless MOSFET with drain and source extensions

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits.

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.

Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor.

The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of Ioff than that in JL planar TFTs. The measured of −1.34 mV/°C in JL GAA nanosheet TFTs has smaller temperature dependence than that of −5.01 mV/°C in JL planar TFTs.

(Invited) Gate-All-Around Ge FETs

- High performance Ge inversion (INV) and junctionless (JL) GAAFETs are demonstrated. The (111) sidewall-enhanced Ge GAA nFETs show 2x enhanced Ion of 110 μA/μm at 1V with respect to the devices with near (110) sidewalls and subthreshold characteristics of 94 mV/dec. The JL Ge GAA pFETs with fin width (Wfin) down to 27 nm and channel doping (Nch) of 5×1018 cm-3 has Ion/Ioff = 1.5×106, SS = 95 mV/dec, and Ion = 194 μA/μm at VGS - VT = -2V and VDS= -1 V. Introduction For the technology nodes of 10 nm and beyond, the high mobility channels (Ge, and III-V) are required to enhance drive current, and new device architectures (FinFET, tri-gates [1], and GAA FETs [2]) are desired to reduce power. Since the Ge epichannel directly on Si can be a low-cost solution, Ge attracts the most interesting for emergent device integration. The misfits of the bottom Ge can be removal by anisotropic etching. The nearly defect-free Ge channel can be formed for GAA transistors. Experiment The intrinsic and heavily doped p-type epi-Ge layer were grown on SOI by the RTCVD for INV and JL devices, respectively. The Ge fins were patterned and formed by anisotropic etching with Cl2/HBr-based plasma to etch away the high defective Ge near Ge/Si interface. The floating Ge fin on SOI was made due to the higher etching selectivity of Ge than Si and the enhanced etching rate by the defects. After the Al2O3/GeO2 gate stack formation, the contact electrodes were deposited and defined. For INV devices, the S/D were implanted with P (1×1015, 18 keV) and activated at 550°C for 30s. For JL devices, The Nch of 5×1018 cm-3 was in-situ doped by PH3 flow. Results and Discussions Since the mobility of (111) Ge is 2 times than (100) Ge, the Ge fin with (111) sidewalls are fabricated to take the advantage of the sidewall enhanced mobility. Thetransfer characteristics of the INV Ge GAA nFETs with the Wfin of 58 nm and the Lg of 350 nm are shown in Fig. 1. Thanks to the GAA structure and the removal of the defect region, the SS of ~ 94 mV/dec and Ion/Ioff of 1.6× 104 at VDS = 0.05V is achieved. The 2x enhancement of the Ion is also observed for the Ge GAA nFET with (111) sidewalls relatively to the Ge FinFET with ~(110) sidewalls. The EOT of 5.5nm obtained from planar devices, and Dit of 1×1012cm-2eV-1 extracted from the simulation. The TEM image of Ge fin with (111) sidewall is shown in the inset of Fig. 1.Thetransfer characteristics of the JL Ge GAA pFETs with the Wfin of 27 nm and the Lg of 250 nm are shown in Fig. 2. The SS of ~ 95 mV/dec and Ion/Ioff of 1.5×106 is achieved for the Nch of 5×1018 cm-3. The Dit of 1×1012 cm-2eV-1 and the EOT of 10 nm are responsible for the SS, confirmed by numerical simulation of GAA FETs. The drain current at VGS - VT = -2V and VDS = -1 V can reach 290 μA/μm for the device with the Nch of 8×101 9 cm-3 and the Wfin of 9 nm, ~1.4X enhancement of the Ion as compared to Nch = 5×1018 cm-3. Note that the Ion of JL GAA nFETs with the Nch of 1×1019 is compatible with the JL GAA pFETs. As compared to INV Ge GAA pFETs, the device with 27-nm Wfinexhibits 49% mobility improvement at high overdrive voltage. The roll-off of mobility of the INV devices with the increasing inversion carrier density is mainly due to the surface roughness scattering (SRS) [3]. As a result, the JL GAA devices have the better immunity of SRS as compared to the INV devices. Conclusion With the removal of defective Ge near Ge/ Si interface, a defect-free Ge GAAFETs can be integrated on the Si platform. With the (111) sidewall-enhanced mobility, INV Ge GAA nFET is demonstrated to have ~2x enhanced Ion. The JL Ge GAA pFETs are also demonstrated with the SS of 95 mV/dec for the device with Nch of 5×101 8 cm-3 and Ion of 290 μA/μm for the device with Nch of 8×101 9 cm-3. Our results show that Ge GAAFETs is a promising candidate for future CMOS applications. Reference [1] C. Auth et al., 2012 Symp. on VLSI Tech., (2012) p. 131.[2] Shu-Han Hsu et al., 2011 International Electron Devices Meeting (IEDM), (2011) p. 825.[3] H. -S. Lan et al., Appl. Phys. Lett., 99 112109 (2011).

An optimized junctionless GAA MOSFET design based on multi-objective computation for high-performance ultra-low power devices

An analytical investigation has been proposed to study the subthreshold behavior of junctionless gates all around (JLGAA) MOSFET for nanoscale CMOS analog applications. Based on 2-D analytical analysis, a new subthreshold swing model for short-channel JLGAA MOSFETs is developed. The analysis has been used to calculate the subthreshold swing and to compare the performance of the investigated design and conventional GAA MOSFET, where the comparison of device architectures shows that the JLGAA MOSFET exhibits a superior performance with respect to the conventional inversion-mode GAA MOSFET in terms of the fabrication process and electrical behavior in the subthreshold domain. The analytical models have been validated by 2-D numerical simulations. The proposed analytical models are used to formulate the objectives functions. The overall objective function is formulated by means of a weighted sum approach to search the optimal electrical and dimensional device parameters in order to obtain the better scaling capability and the electrical performance of the device for ultra-low power applications.

Numerical Analysis of Nanoscale Junctionless MOSFET Including Effects of Hot-Carrier Induced Interface Charges

In this work, we aim at highlighting the immunity of the junctionless Gate All Around (JLGAA) MOSFET against the induced interface tarps degradation at nanoscale level. In this context, a numerical investigation has been proposed to study the subthreshold behavior of the (JLGAA) MOSFET for ultra-low power applications. Based on 2-D numerical investigation, a small-signal parameters model for nanoscale JLGAA MOSFETs, including the hot-carrier induced interface charge effects, is developed. The numerical analysis has been used to simulate the transconductance and output-conductance in subthreshold region and to compare the performance of the investigated design and conventional GAA MOSFET, where the hot-carrier effects are included. High reliability, low fabrication cost and integration ability make JLGAA MOSFET promising candidate to improve the device reliability for the ultra-low power applications.

Small-Signal Modeling of Gate-All-Around (GAA) Junctionless (JL) MOSFETs for Sub-millimeter Wave Applications

In this paper, we present the radiofrequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-㎚ channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 ㎔. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of Y₂₂-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.