Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

Abstract

A high performance gate-all-around (GAA) junctionless (JL) polycrystalline silicon nanowire (poly-Si NW) transistor with channel width of 12 nm, channel thickness of 45 nm, and gate length of 20 nm has been successfully demonstrated, based on a simplified double sidewall spacer process. Without suffering serious short-channel effects, the GAA JL poly-Si NW device exhibits excellent electrical characteristics, including a subthreshold swing of 105 mV/dec, a drain-induced barrier lowering of 83 mV/V, and a high ${I}_{\rm on} /{I}_{\rm off} $ current ratio of $7\times 10^{8} $ ( $V_{\rm G} = 4$ V and $V_{\rm D} = 1$ V). Such GAA JL poly-Si NW devices exhibit potential for low-power electronics and future 3-D IC applications.