Abstract
The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of Ioff than that in JL planar TFTs. The measured of −1.34 mV/°C in JL GAA nanosheet TFTs has smaller temperature dependence than that of −5.01 mV/°C in JL planar TFTs.
Highlights
The junctionless nanowire transistor (JNT), which contains a single doping species at the same level in its source, drain, and channel, has been recently investigated [1,2,3,4,5,6]
The junctionless (JL) device is basically a gated resistor, in which the advantages of junctionless devices include (1) avoidance of the use of an ultra shallow source/drain junction, which greatly simplifies the process flow; (2) low thermal budgets owing to implant activation anneal after gate stack formation is eliminated, and (3) the current transport is in the bulk of the semiconductor, which reduces the impact of imperfect semiconductor/insulator interfaces
The JL gate-all-around structure (GAA) thin-film transistors (TFTs) with a small variation in temperature performances along with simple fabrication are highly promising for future system-onpanel (SOP) and system-on-chip (SOC) applications
Summary
The junctionless nanowire transistor (JNT), which contains a single doping species at the same level in its source, drain, and channel, has been recently investigated [1,2,3,4,5,6]. The temperature dependence of threshold voltage (Vth) is a parameter when integrated circuits often operate at an elevated temperature owing to heat generation. This effect, accompanied with the degradation of subthreshold swing (SS) with temperature, causes the fatal logic errors, leakage current, and excessive power dissipation. This letter presents a high-temperature operation of JL TFTs with a gate-all-around structure (GAA) for an ultra-thin channel. The JL GAA TFTs with a small variation in temperature performances along with simple fabrication are highly promising for future system-onpanel (SOP) and system-on-chip (SOC) applications
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