Junction-gate Field-effect Transistor Research Articles

Design of 6 GHz Variable-Gain Low-Noise Amplifier Using Adaptive Bias Circuit for Radar Receiver Front End

This paper presents a variable-gain low-noise amplifier (VGLNA) based on an adaptive bias (ADB) circuit for the radar receiver front end. The ADB circuit processes the signal separated by a coupler at the LNA output port. First, the ADB circuit rectifies the coupled signal into positive DC voltage through a rectifier, which is then inverted to control a junction-gate field-effect transistor (JFET). The voltage-controlled current of JFET flows through a voltage-divider network and finally produces the DC biasing voltage for the BJT base termination, which decreases with the increase in the input RF power. The proposed VGLNA operates automatically in high gain at low input power and low gain at high input power, providing a wider dynamic range as compared to the constant-bias counterpart. For validation, a prototype is fabricated and measured at 6 GHz. As observed, the base biasing voltage generated by the ADB circuit is changed from 858 mV to 798 mV as the input power increases from −50 dBm to 0 dBm. As a result, the dynamic range represented by the input P1dB point (IP1dB) has an increase of 6.5 dB, while LNA still maintains a high gain of 15.15 dB at low input power.

A 100-Mrad (Si) JFET-Based Sensing and Communications System for Extreme Nuclear Instrumentation Environments

Dry cask storage is one of two storage methods approved by the U.S. Nuclear Regulatory Commission for spent fuel after removal from reactor cores. Dry casks consist of a stainless steel canister enclosed in a concrete overpack to contain the hazardous radioactive spent fuel rods and provide radiation shielding. Monitoring spent fuel storage casks is desired to ensure the safe containment of the enclosed spent fuel, but is very difficult due to the related harsh temperature and radiation environment. The sensors and associated electronics to monitor temperature, pressure, and/or radiation need to survive high temperatures and radiation doses for extended time periods. For this reason, there is a severe need for radiation-hardened electrical systems that survive well beyond the existing capabilities of commercially available radiation-rated electronic components, which have primarily been developed for space applications. Junction-gate field-effect transistor (JFET) devices are inherently radiation hardened [exceeding 100 Mrad (Si)]. When JFETs are used as building blocks for sensing and communication electronics (i.e., oscillators, amplifiers, filters, and mixers), inherently radiation-hardened circuits can be achieved. To this end, JFET-based radiation-hardened electronics interfacing with cask-embedded sensors capable of driving modulated sensor signals through a stainless steel barrier were designed and tested at a dose rate of approximately 500 krad/h (Si) to beyond a 200-Mrad (Si) total ionizing dose. After 200 Mrad (Si), the sensor and communication circuit signals were correctly decoded at the receiver despite oscillator drift. The results from this experiment demonstrate the potential for creating more complex radiation-hardened JFET-based electrical systems for nuclear environments.

Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally <small>off</small> and has a specific <small>on</small>-resistance smaller than that of 1.2-kV SiC <small>mosfets</small>. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power <small>mosfets</small> (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a <small>mosfet</small> driver with a large gate resistance or an <i>RC</i>-interface driver. These drivers turn <small>on</small> the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC <small>mosfet</small>s. Additionally, the <i>RC</i>-interface driver was shown to outperform the <small>mosfet</small> driver for vertical GaN JFETs. The learning about normally <small>off</small> GaN JFETs was applied to a study of commercial normally <small>on</small> SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.

Electronic Sensing Platform (ESP) Based on Open-Gate Junction Field-Effect Transistor (OG-JFET) for Life Science Applications: Design, Modeling and Experimental Results.

This paper presents a new field-effect sensor called open-gate junction gate field-effect transistor (OG-JFET) for biosensing applications. The OG-JFET consists of a p-type channel on top of an n-type layer in which the p-type serves as the sensing conductive layer between two ohmic contacted sources and drain electrodes. The structure is novel as it is based on a junction field-effect transistor with a subtle difference in that the top gate (n-type contact) has been removed to open the space for introducing the biomaterial and solution. The channel can be controlled through a back gate, enabling the sensor’s operation without a bulky electrode inside the solution. In this research, in order to demonstrate the sensor’s functionality for chemical and biosensing, we tested OG-JFET with varying pH solutions, cell adhesion (human oral neutrophils), human exhalation, and DNA molecules. Moreover, the sensor was simulated with COMSOL Multiphysics to gain insight into the sensor operation and its ion-sensitive capability. The complete simulation procedures and the physics of pH modeling is presented here, being numerically solved in COMSOL Multiphysics software. The outcome of the current study puts forward OG-JFET as a new platform for biosensing applications.

Chirality detected in Hartley\u2019s electronic oscillator

Chirality is an elusive asymmetry important in science and technology and confined mainly to the quantum realm. This paper reports the observation of chirality in a classical (that is, not quantum) scenario, namely in stability diagrams of an autonomous electronic oscillator with a junction-gate field-effect transistor (JFET) and a tapped coil. As the number of spikes (local maxima) of stable oscillations changes along closed parameter paths, they generate two types of intricate structures. Surprisingly, such pair of structures are artful images of each other when reflected on a mirror. They are dual chiral pairs interconnecting families of stable oscillations in closed loops. Chiral pairs should not be difficult to detect experimentally. This chirality is conjectured to be a generic property of nonlinear oscillators governed by classical (that is, not quantum) equations.

Ubiquity of ring structures in the control space of complex oscillators.

We report the discovery of two types of stability rings in the control parameter space of a vertical-cavity surface-emitting semiconductor laser. Stability rings are closed parameter paths in the laser control space. Inside such rings, laser stability thrives even in the presence of small parameter fluctuations. Stability rings were also found in rather distinct contexts, namely, in the way that cancerous, normal, and effector cells interact under ionizing radiation and in oscillations of an electronic circuit with a junction-gate field-effect transistor (JFET) diode. We argue that stability-enhancing rings are generic structures present in the control parameter space of many complex systems.

Huang-Pair: A New High Voltage Diode Concept and Its Demonstration

The Huang-Pair is a novel hybrid diode concept based on the integration of a low forward voltage drop, low voltage rating diode with a high voltage majority carrier switch, such as a silicon carbide (SiC) Junction gate field-effect transistor (JFET). A 1200 V Huang-Pair is developed to demonstrate the concept in which a low voltage Si diode is paired with a 1200 V SiC JEFT, resulting in a low-forward voltage, low reverse recovery high voltage diode. The Huang-Pair is a two terminal device and its performance tradeoff between forward voltage drop, leakage current, and reverse recovery can be conducted between two discrete devices, which is more flexible. The Huang-Pair concept can also be realized by SiC MOSFET and gallium nitride MOSFET, and it can be applied to different voltage classes.

Cascode GaN/SiC: A Wide-Bandgap Heterogenous Power Device for High-Frequency Applications

Wireless power transfer systems and plasma generators are among the increasing number of applications that use high-frequency power converters. Increasing switching frequency can reduce the energy storage requirements of the passive elements that can lead to higher power densities or even the elimination of magnetic cores. However, operating at higher frequencies requires faster switching devices in packages with low parasitics. Wide-bandgap (WBG) power devices, such as gallium nitride (GaN) and silicon carbide (SiC) devices, have high-critical fields and high-thermal conductivity that make them good candidates for efficient high-voltage and high-frequency operations. Commercially available GaN and SiC devices have ratings targeting different applications. Lateral GaN devices dominate in lower voltage ( $C_{\text{oss}},C_{\text{iss}}$ ), which make them easy to drive at high frequencies. On the other hand, vertical SiC devices are often used in high-voltage and low-frequency applications since they have higher blocking voltages and larger gate charge than their GaN counterparts. As a result, SiC devices usually require high power and complicated gate drive circuitry. Recent work shows that in both GaN and SiC devices, losses in device $C_{\text{oss}}$ can exceed the conduction losses at high-switching frequencies and relatively high voltages under zero-voltage-switching conditions. Moreover, the $C_{\text{oss}}$ energy loss ( $E_{\text{oss}}$ ) per switching cycle increases with frequency in GaN devices but remains roughly independent of frequency in SiC devices. This means that at high frequencies, SiC devices can be preferable due to their smaller $C_{\text{oss}}$ energy loss even when taking into consideration the complexity of the gate drive circuit. In this article, we present a WBG high-voltage cascode GaN/SiC power device, combining the advantages of both a GaN and an SiC device—namely, simple gate drive requirements, $E_{\text{oss}}$ loss per cycle roughly independent of frequency, and relatively high-voltage blocking capability. Comparing this cascode GaN/SiC device with an SiC mosfet and a SiC junction gate field-effect transistor of similar voltage ratings and $R_{ds,{\text{ON}}}$ , we find that the inverter using the cascode GaN/SiC device has the highest efficiency and simplest auxiliary gate drive circuitry. Finally, integrating the cascode GaN/SiC device has the potential benefits of achieving lower $C_{\text{oss}}$ losses, higher device ratings, and better heat removal capability.

A low-noise resonant input transimpedance amplified photodetector

We present the design and characterization of a low-noise, resonant input transimpedance amplified photodetector. The device operates at a resonance frequency of 90 MHz and exhibits an input referred current noise of 1.2 pA/Hz—marginally above the theoretical limit of 1.0 pA/Hz set by the room temperature Johnson noise of the detector’s 16 kΩ transimpedance. As a result, the photodetector allows for shot-noise limited operation for input powers exceeding 14 µW at 461 nm corresponding to a noise equivalent power of 3.5 pW/Hz. The key design feature which enables this performance is a low-noise, common-source junction gate field-effect transistor amplifier at the input which helps to reduce the input referred noise contribution of the following amplification stages.

A SiC JFET-Based Solid State Circuit Breaker With Digitally Controlled Current-Time Profiles

DC distribution networks are able to effectively improve the energy efficiency and easy integration of distributed generations. However, the reliable dc circuit breaker is an essential requisite for the wide application of dc power. This paper proposes a self-powered solid-state circuit breaker (SSCB) with a digitally controlled current–time profile for both ultrafast short-circuit protection and overcurrent protection. The fault detection unit detects short-circuit or overcurrent conditions by sensing the sampling resistance voltage and delivers these voltage signals to a low-cost microprocessor to realize the protection operation of the SSCB. A pulsewidth modulation (PWM) current limiting protection method with time interval $T_{d}$ is proposed to avoid nuisance tripping caused by inrush current during power electronic load startup. The time interval is properly selected based on the transient thermal properties of silicon carbide (SiC) junction gate field-effect transistors (JFETs). In order to verify the dynamic response of the SSCB, a SiC JFET-based circuit breaker prototype is designed and fabricated for result confirmation.

Lateral GaN Jfet Devices on Large Area Engineered Substrates for Robust Power Switching

GaN-based power switching devices are of significant interest for high efficiency power conversion circuits in medium voltage applications. However, there are still significant challenges preventing mass production and widespread adoption. In particular, lateral HEMT devices lack avalanche capability for rugged power switching, vertical device technology is not mature, the manufacturing cost associated with small diameter substrates is relatively high, and CTE mismatch issues create limitations on epi thickness as well as bow issues for GaN-on-Si. As a scalable substrate solution, Qromis, Inc. has developed commercial substrates designated QST™ which are engineered to be thermally matched to GaN, enabling thick epitaxial layers capable of >1kV devices on 200 mm diameter wafers suitable for fabrication in a CMOS fabrication facility. Taking advantage of this platform, we present a GaN-based lateral junction gate field effect transistor (JFET) device structure for robust power switching. The p-GaN gate functions to collect secondary holes while a second buried p-GaN blocking layer is implemented to pull the electric field below the surface as in a Reduced Surface Field (RESURF) structure. Unlike a HEMT process, the LJFET epi design and process sequence requires appropriate design of the doping in the buffer, gate, and channel layers for charge balancing, and additional process modules for N+ doping for source/drain contact (via ion implantation), low-damage p+ etching to define the gate, and N implantation to partially compensate the p- layer for field management. These steps have been independently optimized. Device testing indicated high current capability (>1A) in large gate width devices and high current density (~200 mA/mm) in smaller devices. The discrepancy is attributed to a processing issue creating spreading resistance in the ohmic contacts indicating a need for thick metallization. Gate continuity was tested by electroluminescence from the forward biased p-n junction, and breakdown tests indicated >1kV blocking capability with low leakage current. In summary, a conceptual prototype for a lateral GaN JFET device was demonstrated experimentally with promising current density and breakdown performance.

New Design of PI Regulator Circuit Based on Three-Terminal Memristors

Three-terminal memristors (MRs), extended from two-terminal ones, have been reported to have strong controllability and thus a wide application potential. In this paper, two three-terminal MR emulators are designed based on the junction gate field-effect transistor (JFET) and the operational amplifier (op amp), respectively, aiming to control the memductance quantitatively by adjusting the voltage applied on the third terminal. To obtain adjustable control parameters, a proportional-integral (PI) controller was designed based on the op amp-based three-terminal MR emulator. Then, the proposed emulators and controller were simulated repeatedly. The simulated results agree well with the theoretical analysis, revealing the good performance and feasibility of our design. The research findings shed new light on improving the controllability of controllers.

Noise of a JFET Charge Amplifier for Piezoelectric Sensors

A comprehensive noise model of a junction gate field-effect transistor (JFET) charge amplifier is presented for applications with piezoelectric sensors. Based on this previously reported amplifier structure, a noise equivalent circuit is derived and discussed. Universal noise gain expressions for each of the twelve considered noise sources are given. By means of an analytical description of the charge amplifier’s noise behavior, the design and optimization of such preamplifiers for various capacitive microelectromechanical sensor systems will be distinctly simplified. Calculations of the noise floor are compared with measurements with a cantilever-type magnetoelectric sensor and with the performance of a so far commonly utilized basic charge amplifier. With the JFET charge amplifier a noise reduction of approximately 22 dB is achieved in the vicinity of the utilized sensor’s resonance frequency of 7.45 kHz. The reported amplifier is the first which has no negative influence on the total noise level of a resonant magnetoelectric sensor system.

Design optimisation of self‐powered gate driver for ultra‐fast DC solid‐state circuit breakers using SiC JFETs

Solid-state circuit breakers (SSCBs) inherently have excellent protection performance, thus they are popular for DC distribution protection. However, the safety and reliability of the SSCBs are limited by the rapid response ability of their own gate drivers. In this study, a self-powered SSCB with a normally-on silicon carbide (SiC) junction gate field-effect transistor (JFET) is proposed as the solid-state switch, whose gate drivers are optimised as well. First, both an optimised fault detection circuit and a designed forward–flyback DC/DC converter of the SSCB gate driver have been presented to achieve fast protection during the course of fault isolation. Then, the detailed analyses of the gate driver circuit parameters effect on protection speed are further investigated based on circuit theory and MATLAB calculation. In order to compare and analyse the dynamic responses of the SSCB with and without optimisation, the actual interruption tests of the fabricated SiC JFET circuit breaker prototype and the employed prototype 400 V DC distribution system have been carried out. The results show that the implementation approach is able to improve protection speed for the SSCBs within the order of a few microseconds.

Guest Editorial Special Issue on Wide Bandgap Power Devices and Applications

Wide bandgap (WBG) power devices, e.g., silicon carbide (SiC) and gallium nitride (GaN)-based diodes, metal-oxide field-effect transistors (MOSFETs), junction gate field-effect transistors, bipolar junction transistors, insulated gate bipolar transistors (IGBT), high-electron-mobility transistors, etc., are poised to change the landscape of power electronics industry. Ideally, these devices are expected to have better efficiency, higher temperature tolerance, and higher voltage blocking capability than their silicon (Si) counterparts. Emerging applications of WBG devices include ultrahigh power density switching power supplies, high-temperature converters and inverters for automobiles, ships, and airplanes, medium-voltage and high-speed motor drives, voltage source converter-based high-voltage dc systems, high-frequency power supplies for medical devices and wireless charging, etc. But to achieve the expected superior system performance with WBG devices, innovations are needed not only in materials and devices but also in circuit topology, and systems design and optimization.

A Class-E Direct AC–AC Converter With Multicycle Modulation for Induction Heating Systems

Induction heating systems are the technology of choice in many industrial, domestic, and medical applications due to its high performance. The core component of such systems is the power supply, which is usually composed of a rectifier stage and a resonant inverter. In order to simplify and further optimize the performance of the power supply, a class-E direct ac-ac converter featuring multicycle modulations is proposed in this paper. The proposed converter is composed of two switching devices that enable the direct ac-ac conversion. Single- and multicycle operation modes have been analytically described to prove the benefits, in terms of peak voltage reduction and output power control capabilities. A prototype featuring SiC junction-gate field-effect transistor devices, which perfectly fit these applications, has been designed and built to prove the feasibility of the proposed converter. The experimental results match the analytical results and validate the benefits of this converter.

Gate-Drive Voltage Design for 600-V Vertical-Trench Normally-Off SiC JFETs toward 94% Efficiency Server Power Supply

A gate-drive voltage for a normally-off silicon-carbide vertical-trench junction-gate field-effect transistor (JFET) was designed for a server power supply with 94% efficiency. Since the on-state resistance of the JFET is strongly depends on the gate voltage and a large gate-leakage current between the gate electrode and source flows by applying an excessively high-gate voltage, we therefore must set an adequate turn-on gate-drive voltage to suppress the increase in power loss. The optimum gate-drive voltage design was estimated to be 2.1 V, resulting in a high efficiency of 94% even with a gate-drive voltage variation of ±0.3 V.

All-in-One Photovoltaic Power System: Features and Challenges Involved in Cell-Level Power Conversion in ac Solar Cells

Power converters constructed from discrete components are difficult to mass produce, and their installation requires a significant labor cost for the proper interconnection among the panel, inverter, and grid. Several critical applications, such as portable power stations (for use on a battlefield or scientific expedition), will require key attributes from a photovoltaic (PV)-based power system, such as modularity, high reliability, and quick set-up time. Therefore, a paradigm shift in the design of the entire PV power system is needed to mitigate this need. To increase the converter reliability and portability, the active and passive elements of a power converter [especially capacitors and active switches such as metal-oxide-semiconductor field-effect transistors (MOSFETs), junction gate field-effect transistors (JFETs), or insulated-gate bipolar transistors (IGBTs)] could be embedded on the same substrate material used for fabricating the p-n junctions in the PV panel. To the authors' knowledge, there is no prior work in cell-level power conversion with embedded converters, and therefore this project idea could be considered "outside the box." A novel fabrication process along with experimental results are presented in this article, demonstrating the integration of PV cells and major components needed to build a power converter on the same substrate/wafer. Because of the cell-level power conversion, PV panels constructed from these cells are likely to be immune to partial shading and hot-spot effects. In addition, the effect of light exposure on converter switches has been analyzed to understand the converter behavior at various illumination levels. Simulation and experimental results have been provided to support this analysis. In addition to process-related challenges and issues, the justification of this integration is explained by achieving higher reliability, portability and complete modular construction for PV-based energy harvesting units.

Development of a SiC JFET-Based Six-Pack Power Module for a Fully Integrated Inverter

In this paper, a fully integrated silicon carbide (SiC)-based six-pack power module is designed and developed. With 1200-V, 100-A module rating, each switching element is composed of four paralleled SiC junction gate field-effect transistors (JFETs) with two antiparallel SiC Schottky barrier diodes. The stability of the module assembly processes is confirmed with 1000 cycles of −40 °C to +200 °C thermal shock tests with 1.3 °C/s temperature change. The static characteristics of the module are evaluated and the results show 55 mΩ on-state resistance of the phase leg at 200 °C junction temperature. For switching performances, the experiments demonstrate that while utilizing a 650-V voltage and 60-A current, the module switching loss decreases as the junction temperature increases up to 150 °C. The test setup over a large temperature range is also described. Meanwhile, the shoot-through influenced by the SiC JFET internal capacitance as well as package parasitic inductances are discussed. Additionally, a liquid cooled three-phase inverter with 22.9 cm × 22.4 cm × 7.1 cm volume and 3.53-kg weight, based on this power module, is designed and developed for electric vehicle and hybrid electric vehicle applications. A conversion efficiency of 98.5% is achieved at 10 kHz switching frequency at 5 kW output power. The inverter is evaluated with coolant temperature up to 95 °C successfully.

Saturation Current and On-Resistance Correlation during During Repetitive Short-Circuit Conditions on SiC JFET Transistors

This letter presents a correlation between the reduction of the saturation current level and increase of on-state resistance and the top-metal ageing of normally ON SiC junction gate field effecttransistors. For this study, ageing has been obtained using repetitive short-circuit operations. Among monitored parameters during ageing, on-state resistance and short-circuit current level are those, which have the strongest evolution. The top-metal degradation has been characterized via the on-state resistance measurement during ageing. In particular, we clearly show that the top-metal restructuration due to ageing leads to an additional voltage drop between gate and source terminals and results to a lower gate-source junction voltage.