Junction Field Effect Transistor Research Articles

Ultra‐Low Power and Reliable Dynamic Memtransistor Based on Charge Storage Junction FET with Step‐Wise Potential Barrier for Energy‐Efficient Edge Computing Framework

AbstractThe emergence of technologies such as Artificial Intelligence (AI) and the Internet of Things (IoT) has ushered in the era of big data. The demand for low‐power hardware systems and efficient algorithms has become more imperative. In this study, an ultra‐low‐power dynamic memtransistor based on the charge storage junction Field‐Effect Transistor (FET) with a step‐wise potential barrier is developed. A simple yet efficient device structure allows for analog programming and spontaneous relaxation. The device demonstrated fast speed (tens of nanoseconds (ns)) and low current (in picoamperes (pA)), resulting in ultra‐low programming power (in attojoules (aJ)). Furthermore, the device exhibited high reliability, with a 0.4% cycle‐to‐cycle variation and endurance over 107 pulses, owing to its non‐structural destructive operation process. An operation scheme is developed that enables read on/off and program/inhibition mode for 2T (1 memtransistor‐1 selecting transistor) array. The capability to distinguish temporal data using the device's spontaneous relaxation characteristics is demonstrated. A reservoir computing (RC) system framework is constructed using simulation and verified that the dynamic memtransistor can extract features efficiently from a hand‐written digit dataset. It is anticipated that the developed dynamic memtransistor, with its distinctive temporal characteristics, will play a pivotal role in developing a novel low‐power computing framework.

Study of drain induced channel effects in vertical GaN junction field-effect transistors

Study of drain induced channel effects in vertical GaN junction field-effect transistors

Process-in-Memory realized by nonvolatile Task-Scheduling and Resource-Sharing XNOR-Net hardware Accelerator architectures

Due to the success of artificial intelligence systems in solving complex problems, these systems have been investigated in many applications. There is an increasing demand for these systems in many new applications. The XNOR-Net, a binary neural network, is a promising candidate for implementing these systems in devices with limited power and hardware resources. Efficient hardware implementation of XNOR-Nets is critical and has been widely investigated in recent research. In this paper, a resource-sharing gate and architecture and a task-scheduling gate and architecture have been proposed. To reduce power consumption, the proposed nonvolatile logic-in-memory gates are designed based on the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistor (CNTFET) devices. Using the proposed resource-sharing gate for hardware implementation of XNOR-Net minimizes the number of flip-flops, power consumption, PDP, and area by at least 75%, 75%, 60%, and 42%, respectively, as compared to its state-of-the-art counterparts. Also, using the proposed task-scheduling design to implement the XNOR-Net on 2, 4, and 8 datasets, the power consumption is reduced by at least 24%, 54%, and 65%, respectively, compared to its state-of-the-art counterparts .

High-responsivity, high-detectivity, broadband infrared photodetector based on MoS2/BP/MoS2 junction field-effect transistor

Sensitivity stands as a critical figure of merit in assessing the performance of a photodetector and can be characterized by two distinct parameters: responsivity or detectivity. Simultaneous optimization of these two parameters is essential to ensure the applicability of a single detector across various scenarios, yet it remains a persistent challenge for mid-infrared photodetector. Here, we demonstrate that the construction of a photoconductive detector based on a MoS2/BP/MoS2 npn junction field-effect transistor configuration can effectively balance the tradeoffs between photoresponsivity and detectivity. In this device, the black phosphorus layer serves as the channel, while the top and bottom MoS2 layers act as photogates to boost the photocurrent. Consequently, a high-performance room-temperature-operating mid-infrared photodetector with a responsivity and detectivity reaching 9.04 A W−1 and 5.36 × 109 cm Hz1/2 W−1 (1550 nm), and 7.25 A W−1 and 4.29 × 109 cm Hz1/2 W−1 (3600 nm) is achieved. Our study provides an alternative structural design, enabling the applications of mid-infrared photodetectors across multiple scenarios.

Thinning Solution‐proceed 2D Te for p‐ and n‐channel Junction Field Effect Transistor with High Mobility and Ideal Subthreshold Slope

AbstractTwo‐dimensional non‐layered tellurene (Te) can serve as a promising candidate in transistor applications because of its high carrier mobility and air stability. However, it is still quite challenging in aspect of ultra‐thin channel and gate‐control ability in conventional metal‐oxide‐semiconductor field‐effect transistor architecture. This work proposes a facile thinning strategy for solution‐proceed Te flakes and fabricates a junction field‐effect transistor (JFET) architecture, that has well addressed the above‐mentioned two issues. Through a mild oxidative thinning process, the post‐growth Te flakes are thinned from bulk to few‐layer, guaranteeing the highly efficient electrostatic doping as a transistor channel. Then, a four‐terminal JFET‐based on p‐Te and n‐ReS2 is designed, achieving a multifunctional integration of rectification diode, p‐ and n‐channel transistor in one single device. By accessing different contact scheme, the ReS2/Te p‐n diode is explored with a rectification ratio of 103, the p‐channel JFET exhibits a high hole mobility of 317.6 cm2V−1s−1, ideal low subthreshold swing of 84 mV dec−1. While the n‐channel JFET is obtained with electron mobility of 67.6 cm2 V−1s−1 and SS of 229 mV dec−1. Both p‐ and n‐channel devices showcase clear saturation characteristic with ultra‐small pinch‐off voltage (≈0.4 V), which is crucial for low‐power logical and integrated circuit applications.

Tunable optoelectronic response in van der Waals heterojunction transistors for artificial visual recognition

Optoelectronic synaptic transistors are advantageous in in-memory light sensing for artificial neural networks. Herein, optoelectronic synaptic junction field-effect transistors (JFETs) based on a Ga2O3/MoS2 heterojunction are fabricated. The devices exhibit robust electrical performances, including a high on/off ratio of 108, a low subthreshold swing of 69 mV dec−1, and a high output current of 3.4 μA μm−1. An inverter and a NAND gate are constructed based on the dual-gated configuration, with the inverter showing a high voltage gain of 28 and the near-ideal noise margin of 90.4%. Additionally, the devices demonstrate outstanding optoelectronic performances benefiting from the strong light–matter interactions of MoS2. Typical synaptic plasticities, including short-term plasticity, long-term plasticity, and spiking-rate-dependent plasticity, are simulated by applying the light pulses. Furthermore, metaplastic excitatory postsynaptic current, metaplastic facilitation of long-term potentiation and transition from potentiation to depression are also readily demonstrated. The artificial neural network, in which neurons are interconnected through our proposed optoelectronic synaptic transistors, achieves a high accuracy of 89.8% in recognizing handwritten digits. This work provides insight into the design of an optoelectronic synapse based on JFETs.

A hybrid amplifier topology for low‐noise direct‐coupled front ends

SummaryHybrid amplifiers combine discrete transistors with operational amplifiers (OAs) achieving superior characteristics compared with commercially available OAs, while keeping simple structures and a reduced number of parts. A single‐ended amplifier topology based on a junction field‐effect transistor (JFET) is proposed as a means of achieving very low input noise levels, both in current and voltage. It is direct‐coupled and allows to place a high‐pass filter at its input to preserve input range, or at its output to optimize noise. The proposed topology results in a low input capacitance and low input‐current noise, making it suitable for applications where multiple amplifiers are connected in parallel to achieve ultra‐low noise levels. The amplifier's gain is set by a resistor ratio, being suitable for instrumentation front ends. The circuit analysis and design equations are provided to adapt it for different applications and, as an example, an amplifier with a gain of 40 dB and a bandwidth from DC to 1 MHz was designed, built, and tested. The dominant noise contribution of the amplifier was the JFET (a JFE2140 device), featuring an input noise voltage of , that is reduced to when two amplifiers are connected in parallel.

Precision RMS-to-DC Converter

The developed model of a resistive-transistor thermoelectric converter, the technique for identifying its parameters and the results of circuit simulation using the proposed model of an RMS-DC converter are considered. The electrical circuit of the RMS-DC converter is given, the dependences of the conversion error on the input voltage level obtained by circuit modeling, on the basis of which the main requirements for reducing the error are formulated. The application of operational amplifiers of the OAmp11.2 type with input junction field-effect transistors, previously developed on the master slice array МН2ХА031, makes it possible to implement a precision RMS-DC converter in the form of a microassembly containing two crystals of the ПН001 thermoelectric converter, one МН2ХА031 crystal with a signal processing circuit and external filter capacitors. Circuit simulation showed that such a converter remains operational at an absorbed dose of gamma radiation equal to 1 Mrad and exposure to a neutron fluence of 1 ⋅ 1013 n/cm2 .

A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V F·C res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V F·C res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm−1 while elevating the BV to 16.6 kV. A new FOM of V F·C res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V F·C res FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.

Advancements And Applications of Field-Effect Transistors in Modern Electronics

Field-Effect Transistors (FETs) have evolved as fundamental semiconductor devices pivotal to modern electronics. This paper provides an extensive overview of FETs, encompassing their definition, classification, and historical development. FETs, such as Junction Field-Effect Transistors (JFETs) and Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), are explained, highlighting their distinct characteristics and applications. Additionally, innovative FET variants like Piezoelectric Field-Effect Transistors (PiezoFETs) and High Electron Mobility Transistors (HEMTs) are explored for their unique attributes and applications. The paper underscores the critical role FETs play in diverse sectors, including low-power digital circuits, RF applications, biosensors, and flexible electronics. It emphasizes their contributions to achieving ultra-low power consumption, rapid analysis, and real-time, label-free diagnostics. The collaborative efforts of experts from various disciplines are emphasized as essential for optimizing FET-based biosensors. Furthermore, the paper emphasizes the exciting potential of graphene-based FETs (G-FETs) in Bioelectronics and their ability to revolutionize point-of-care diagnostics. G-FETs' scalability, low-cost manufacturing, and superior properties make them a promising choice for future healthcare applications.

Nanodevice simulations and electronic transport properties of a two-dimensional PbBr2 monolayer

Two-dimensional (2D) wide bandgap semiconductors are promising blocks for applications in photodetections, spintronics and high energy radiation detection. Here, we probe the mechanical, biaxial strain-relate, electronic transport, and optoelectronic properties of PbBr2 monolayer with wide bandgaps using first-principles calculations. The 2D Young's modulus of PbBr2 monolayer is determined to be 14.68 N m−1 and the shear modulus is calculated to be 5.83 N m−1 at 300 K, revealing that PbBr2 monolayer is mechanically more flexible than other 2D materials, such as hexagonal-BN and MoB2. Interestingly, a specific forbidden bandwidth can be obtained by implementing a suitable strain on PbBr2 monolayer, and such effect leads to indirect bandgap semiconductor properties. Furthermore, various PbBr2 monolayer nanodevices, including p-n junction diodes, p-i-n junction field-effect transistors (FETs), and phototransistors, are designed and explored to investigate their transport properties. A variety of excellent transport properties, including prominent unidirectional transport, remarkable electrical anisotropy, obvious field-effect property, strong photoelectric response, and prominent absorption characteristics in the ultraviolet region, have been observed in these nanodevices. Our results unveil the multifunctional nature and superior performance of PbBr2 monolayer and suggest a practical configuration for the experimental realization in next-generation semiconductor nanodevices.

(Invited) In-Situ MOCVD Etching of GaN Using XeF2 for Selective-Area-Epitaxial-Regrowth of p-Type GaN for High Voltage PN Diodes

PN diodes with multi-kilovolt breakdown voltages have been demonstrated to great than 6 kV in GaN, validating the device potential predicted by the intrinsic material properties of III-nitride semiconductors. However, power control circuits also require switching transistors such as junction field effect transistors (JFETs) and practical diodes such as merged PIN Schottky (MPS) diodes. Such devices usually employ selective areas of p-type semiconductor surrounded by n-type material and require the formation of PN junctions with low reverse leakage current. Selective-area p-type doping in Si and SiC based power devices is typically achieved using implantation and thermal annealing to form the p-type areas. Ion implantation of Mg in GaN has demonstrated p-type conductivity, but this process requires specialized equipment for the high-pressure and high-temperature activation of Mg dopants. We have investigated selective-area-regrowth (SArG) to epitaxially grow p-type GaN as an alternative to dopant implantation. Successful PN diode formation by SArG requires a process to remove residual crystalline damage resulting from the ex-situ inductively coupled plasma (ICP) etch typically used to form the p-well, as well as a method to remove the elevated level of Si found at the regrowth interface of a surface that had been exposed to air. For the case of SArG of p-GaN on air-exposed, blanket ICP etched n-type GaN, we present the novel use of a fluorine-based precursor (XeF2) for in-situ etching of GaN in the MOCVD chamber. Unlike chlorine (TBCl and CCl4) and bromine (CBr4) -based precursors we have studied; we obtained a smooth surface following in-situ fluorine etching of air-exposed GaN. Schottky barrier diodes (SBDs) formed by shadow mask evaporation on in-situ fluorine etched n-GaN that had been previously ICP etched showed reverse leakage currents to -40 V that are equal to those of SBDs formed on as-grown n-GaN layers. The in-situ fluorine/ICP etched Schottky diodes had reverse leakage currents more than 3 orders of magnitude lower than those formed on n-GaN layers that had only experienced ICP etching. This suggests that the in-situ fluorine etch was effective at removing the residual damage from the ICP etch process. Furthermore, we discuss the use of in-situ fluorine etching to reduce the concentration of Si at the regrowth interface required to form PN junctions with low reverse leakage current. This work was supported in part by the Advanced Research Projects Agency – Energy (ARPA-E), U.S. Department of Energy under the PNDIODES program directed by Dr. Isik Kizilyalli, and in part by the US Department of Energy (DOE) Vehicle Technologies Office (VTO) under the Electric Drive Train Consortium. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. The views expressed in the presentation do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Research on Low Noise Chopping Amplifier Circuit Based on Feedback Regulation

In order to overcome the limitation of 1/f noise on long-period magnetotelluric sensors, it is necessary to use low-noise chopping technology for signal conditioning. However, the static operating point drift of Junction Field-Effect Transistor (JFET) is difficult to achieve stable amplification with the chopper technology. This paper proposes a low noise amplifier (LNA) with chopper technology based on feedback adjustment. The LNA reduces the turning frequency of the circuit, and maintains the JFET static point. At 375mHz, its noise is 2.55nV/Hz .

1.2 kV SiC MOSFETs with tapered buffer oxide for the suppression of the electric field crowding effect

1.2 kV silicon carbide (SiC) MOSFETs with buffered oxide, which have been developed to reduce the gate–drain charge (Q GD), have the problem that the electric field is crowded at the corners of the buffered oxide. In this paper, 1.2 kV SiC MOSFETs with tapered buffer oxide are proposed to suppress the electric field crowding effect. The devices with tapered buffer oxide having an angle of 40° demonstrate a maximum electric field at the gate oxide in the off-state (E ox,max) of 1.87 MV·cm−1, achieving a 13.4% reduction compared to devices with a conventional structure. Additionally, it is verified that the output characteristics of 1.2 kV SiC MOSFETs can be improved by applying tapered buffer oxide. This is because the junction FET region can be designed with high concentration through the suppression of the electric field of the tapered buffer oxide.

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extremeenvironment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Influence of Gate Depletion Layer Width on Radiation Resistance of Silicon Carbide Junction Field-Effect Transistors

Silicon carbide junction field-effect transistors (SiC JFETs) are promising candidates as devices applicable to radiation conditions, such as the decommissioning of nuclear facilities or the space environment. We investigate the origin of the threshold volage (Vth) shift and hysteresis of differently structured SiC JFETs. A large positive Vth shift and hysteresis are observed for a depletion-type JFET with a larger depletion layer width. With changing the sweep range of the gate voltage and depletion width, the Vth shift was positively proportional to the difference between the channel depth and depletion width (channel depth–gate depletion width). By illuminating the sub-band gap light, the Vth of the irradiated depletion JFETs recovers close to nonirradiated ones, while a smaller shift and hysteresis are observed for the enhancement type with a narrower width. It can be interpreted that positive charges generated in a gate depletion layer cause a positive Vth shift. When they are swept out from the depletion layer and trapped in the channel, this gives rise to a further Vth shift and hysteresis in gamma-irradiated SiC JFETs.

Simulation And Design of a Vertical Gallium Nitride JFET with Dual Lateral Heterojunction Channels

A novel vertical gallium nitride (GaN) junction field-effect transistor (JFET) is reported in this article. Through the setup of dual lateral heterojunction channels in the body, the current density is high while the p-type gallium nitride growth area can be adjusted to easily achieve enhanced mode. Based on the structure parameter settings in this article, through the device simulation software TCAD, and under the condition of selecting the appropriate p-type GaN growth region, the threshold voltage of the device is 1.1 V, the source output current density can reach 7.2 kA/cm2, the breakdown voltage is about 750 V, and the on-resistance is 0.52 mΩ·cm2. Finally, the test circuit is built, and the switching characteristics of the device proposed in this paper are simulated under the consideration of parasitic inductance.

Novel Vertical Fin-Based NiO/β-Ga2O3 Heterojunction Field-Effect Transistor with a Low Ron,sp

In this paper, a novel vertical fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (Fin-HJFET) is proposed and studied by TCAD. Theoretically high conduction band offset () enables Ga2O3 Fin-HJFET to produce electron confinement effect at certain gate bias voltage. According to the simulation results, this effect makes Ga2O3 Fin-HJFET can not only form surface-conducting fin channels that are not available in conventional fin-based junction field-effect transistor (Fin-JFET) but also have a stronger electron accumulation capability than Ga2O3 vertical FinFET due to the deep potential well, which leads to a lower specific on-resistance (). In addition, Ga2O3 Fin-HJFET inherits the advantages of Ga2O3 FinFET as a vertical normally-off device and has a higher breakdown voltage compared to FinFET without field plates due to the protection of the highly doped NiO layer. Particularly, Fin-HJFET with different heterojunction band alignments are also considered and discussed. At last, the parameter influence and future optimization space of this highly promising device are explored, providing guidance for actual device fabrication and future device improvement.

2D Amorphous GaOX Gate Dielectric for β-Ga2O3 Metal-Insulator-Semiconductor Field-Effect Transistors

Beta gallium oxide (β-Ga2O3) is an n-type ultra-wide bandgap semiconductor material with a reported bandgap from 4.5 eV to 4.9 eV. β-Ga2O3 is a frontrunner in the research for next-generation power devices owing to its numerous merits including the wide range of donor doping concentrations, large bandgap, high theroretical value of critical electric field (~8 MV/cm) leading to substantial Baliga’s figure of merit of ~1900, and the low production cost for crystalline wafers. The last is enabled by the commercial development of several bulk growth techniques, namely, melt growth methods including Czochralski and edge-defined film-fed growth, and epitaxial growth. The metal-insulator-semiconductor field-effect transistor (MISFETs) is the most widely used device structure since it often requires less complicated fabrication process and offers better device scaling and faster switching speed than their counterparts such as junction field-effect transistors or bipolar junction transistors. Various dielectric materials, such as silicon dioxide, hafnium oxide, and aluminium oxide, have been explored for incorporation into β-Ga2O3 MISFETs. However, many of the dielectrics require high-temperature and/or high-vacuum processes during fabrication. Recent studies have reported on the self-limiting formation of native oxide film on the surface of liquid gallium at room temperature and the application of the oxide film as a passivation or a dielectric layer in a nano-scale device. In this study, two-dimensional (2D) amorphous gallium oxide (a-Ga2O3) film is fabricated through the liquid gallium squeezing technique and is integrated with a β-Ga2O3 field-effect transistor (FET) to demonstrate an a-Ga2O3/β-Ga2O3 MISFET.In this work, β-Ga2O3 nano-flakes were obtained through mechanical exfoliation and were dry-transferred onto Si/SiO2 substrates. Electron-beam lithography and electron-beam evaporation were performed to define and deposit Ti/Au electrodes, respectively, where rapid thermal annealing was performed afterward to form Ohmic source and drain contacts. Polypropylene carbonate (PPC) solution was spin-coated and baked on a polydimethylsiloxane (PDMS) film, placed on a glass slide for mechanical support, to form a uniform PPC layer on the PDMS film. A liquid gallium droplet was placed on the PPC/PDMS film and was squeezed with a cleaned glass slide to form a uniform 2D a-Ga2O3 layer. The fabricated a-Ga2O3 layer was dry-transferred onto a β-Ga2O3 FET during which temperature of 90 °C was applied to the sample chuck to completely release the PPC layer with the a-Ga2O3 layer from the PDMS layer. The resulting a-Ga2O3/β-Ga2O3 FET was submerged in acetone to remove the PPC layer. The above dry-transfer process of the a-Ga2O3 layer was conducted twice to form double-layered a-Ga2O3 on the β-Ga2O3 FET, before performing electron-beam lithography and electron-beam evaporation to respectively define and deposit the Ni/Au top-gate electrode.The electrical properties of the fabricated device is characterized as a Ni/a-Ga2O3/β-Ga2O3 heterojunction and an a-Ga2O3/β-Ga2O3 MISFET at temperatures of 25 °C, 150 °C, and 250 °C. The Ni/a-Ga2O3/β-Ga2O3 heterojunction of the device shows a clear rectification characteristic with a wider operating voltage compared to those of standard Ni/β-Ga2O3 devices in literatures. The double-layered a-Ga2O3 The a-Ga2O3/β-Ga2O3 MISFET exhibits normally-on n-type conductivity with stable operation at temperatures from 25 °C to 250 °C, where the obtained on/off current ratio and mobility range from 5.3×108 to 4.8×107 and 4.7 cm2/V·s to 6.9 cm2/V·s, respectively. The subthreshold swing and the threshold voltage of the a-Ga2O3/β-Ga2O3 MISFET showed increases and negative shifts at higher temperatures, respectively. This work demonstrates the facile fabrication process of the a-Ga2O3/β-Ga2O3 MISFET and its high-temperature stability through the integration of the 2D amorphous Ga2O3 gate dielectrics with a β-Ga2O3 semiconductor.

Contact-engineered reconfigurable two-dimensional Schottky junction field-effect transistor with low leakage currents

Two-dimensional (2D) materials have been considered promising candidates for future low power-dissipation and reconfigurable integrated circuit applications. However, 2D transistors with intrinsic ambipolar transport polarity are usually affected by large off-state leakage currents and small on/off ratios. Here, we report the realization of a reconfigurable Schottky junction field-effect transistor (SJFET) in an asymmetric van der Waals contact geometry, showing a balanced and switchable n- and p-unipolarity with the Ids on/off ratio kept >106. Meanwhile, the static leakage power consumption was suppressed to 10−5 nW. The SJFET worked as a reversible Schottky rectifier with an ideality factor of ~1.0 and a tuned rectifying ratio from 3 × 106 to 2.5 × 10−6. This empowered the SJFET with a reconfigurable photovoltaic performance in which the sign of the open-circuit voltage and photo-responsivity were substantially switched. This polarity-reversible SJFET paves an alternative way to develop reconfigurable 2D devices for low-power-consumption photovoltaic logic circuits.