Junction Barrier Schottky Diodes Research Articles

Suppression of the Carbon Vacancy Traps and the Corresponding Leakage Current Reduction in 4H-SiC Diodes by Low-Temperature Implant Activation in Combination With Oxidation

Junction barrier Schottky diode fabrication involves multi-folded Al ion implantation for realizing p-type doping. With a new fabrication recipe, we demonstrate that the trade-off between sufficiently high Al acceptor activation and sufficiently low residual concentration of carbon vacancies - acting as free carrier traps - may be resolved applying relatively low temperature anneals (1700°C), followed by the thermal oxidation which leads to in-diffusion of the carbon interstitials from the C-rich sacrifice-oxide/SiC interface. Specifically, we detected two major interconnected factors: suppression of the carbon vacancies and dramatic reduction of the reverse leakage current (by 32 times at -1200 V). The reduction of the reverse biased current is correlated with the removal of the carbon vacancies, interconnected with the Poole-Frenkel emission contribution to the leakage current.

High performance trench diamond junction barrier Schottky diode with a sidewall-enhanced structure

The trench diamond junction barrier Schottky (JBS) diode with a sidewall enhanced structure is designed by Silvaco simulation. Comparing with the conventional trench JBS diode, Schottky contact areas are introduced on the sidewall of the trench beside the top cathode. The sidewall Schottky contact weakens the junction field-effect transistor effect between the trenches to realize a low on-resistance and a high Baliga’s figure of merit (FOM) value. In addition, the existence of the n-type diamond helps to suppress the electric field crowding effect and enhance the reverse breakdown voltage. With the optimal parameters of device structure, a high Baliga’s FOM value of 2.28 GW/cm2 is designed. Therefore, the proposed sidewall-enhanced trench JBS diode is a promising component for the applications in diamond power electronics.

Chip packaging interaction of SiC junction barrier Schottky diode packages

Wide band gap semiconductors are attractive in the electric vehicle industry because of their higher operating temperatures, and lower switching losses than those of silicon semiconductors. However, the electric vehicle industry has driven the development of more reliable semiconductors because of safety issues. Among several reliability issues, the reliability at the chip level can be a challenging problem because chip-related failures are difficult to observe in the early design stage. In this study, the chip package interaction for a silicon carbide (SiC) junction barrier Schottky diode package was investigated to estimate the stresses of the chip layers at the package level. This methodology will help power semiconductor manufacturers perform a robust design of their packages in terms of SiC chip reliability. Moreover, the response surface methodology can be used to establish a correlation between the maximum stresses of the passivation layer and three-wire bonding conditions. This methodology can be used to determine optimal wire-bonding conditions to improve chip reliability.

Schottky contacts on ultra-high-pressure-annealed GaN with high rectification ratio and near-unity ideality factor

We investigate the electrical characteristics of Ni Schottky contacts on n-type GaN films that have undergone ultra-high-pressure annealing (UHPA), a key processing step for activating implanted Mg. Contacts deposited on these films exhibit low rectification and high leakage current compared to contacts on as-grown films. By employing an optimized surface treatment to restore the GaN surface following UHPA, we obtain Schottky contacts with a high rectification ratio of ∼109, a near-unity ideality factor of 1.03, and a barrier height of ∼0.9 eV. These characteristics enable the development of GaN junction barrier Schottky diodes employing Mg implantation and UHPA.

Analysis of Breakdown-Voltage Increase on SiC Junction Barrier Schottky Diode Under Negative Bias Stress

In this study, the increment in the breakdown voltage of a SiC junction barrier Schottky (JBS) diode under negative bias stress (NBS) is investigated. However, when the SiC JBS exhibits an increase in breakdown voltage after NBS, its forward characteristic does not change. The variation in breakdown voltage increases under a higher stress voltage that is close to the breakdown voltage of SiC JBS without stress. Furthermore, the variation in breakdown voltage increases with a higher compliance current and at lower NBS temperature. The electric field of SiC JBS under NBS is simulated to clarify the variation in breakdown voltage under NBS. The electrical characteristics and the simulation of the electric field under NBS demonstrate that the increase in the breakdown voltage of SiC JBS after NBS is induced by the electron injection in the oxide layer of edge termination.

TCAD evaluation of single-event burnout hardening design for SiC Schottky diodes

In this paper, a single-event burnout (SEB) hardening technique for Schottky diodes at a linear energy transfer (LET) value of 0.5 pC/μm (75.5 MeV/mg/cm2) is presented and investigated by 2-D numerical simulations. The simulation results show that, when compared with the conventional junction barrier Schottky (JBS) diode with multiple buffer layers, the proposed structure can significantly reduce the electric field at the metal/SiC interface with the help of the trench, thereby reducing the interface temperature. Moreover, the maximum global temperature of the proposed structure is also reduced. The maximum global temperature of the proposed structure is 1989 K and the temperature at the Schottky contact interface is 439 K for the bias voltage of 1000 V and LET value of 0.5 pC/μm (75.5 MeV/mg/cm2) which shows that the new structure has better SEB performance. In addition, the hardening method proposed in this paper can be applied at different breakdown voltages by adjusting the structural parameters of the device.

Mg-implanted vertical GaN junction barrier Schottky rectifiers with low on resistance, low turn-on voltage, and nearly ideal nondestructive breakdown voltage

Vertical GaN junction barrier Schottky (JBS) diodes with superior electrical characteristics and nondestructive breakdown were realized using selective-area p-type doping via Mg ion implantation and subsequent ultra-high-pressure annealing. Mg-ion implantation was performed into a 10 μm thick Si-doped GaN drift layer grown on a free-standing n-type GaN substrate. We fabricated the JBS diodes with different n-type GaN channel widths Ln = 1 and 1.5 μm. The JBS diodes, depending on Ln, exhibited on-resistance (RON) between 0.57 and 0.67 mΩ cm2, which is a record low value for vertical GaN Schottky barrier diodes (SBDs) and high breakdown (BV) between 660 and 675 V (84.4% of the ideal parallel plane BV). The obtained low RON of JBS diodes can be well explained in terms of the RON model, which includes n-type GaN channel resistance, spreading current effect, and substrate resistance. The reverse leakage current in JBS diodes was relatively low 103–104 times lower than in GaN SBDs. In addition, the JBS diode with lower Ln exhibited the leakage current significantly smaller (up to reverse bias 300 V) than in the JBS diode with large Ln, which was explained in terms of the reduced electric field near the Schottky interface. Furthermore, the JBS diodes showed a very high current density of 5.5 kA/cm2, a low turn-on voltage of 0.74 V, and no destruction against the rapid increase in the reverse current approximately by two orders of magnitude. This work demonstrated that GaN JBS diodes can be strong candidates for low loss power switching applications.

Vertical GaN junction barrier Schottky diodes with near-ideal performance using Mg implantation activated by ultra-high-pressure annealing

We report a kV class, low ON-resistance, vertical GaN junction barrier Schottky (JBS) diode with selective-area p-regions formed via Mg implantation followed by high-temperature, ultra-high pressure (UHP) post-implantation activation anneal. The JBS has an ideality factor of 1.03, a turn-on voltage of 0.75 V, and a specific differential ON-resistance of 0.6 mΩ·cm2. The breakdown voltage of the JBS diode is 915 V, corresponding to a maximum electric field of 3.3 MV cm−1. These results underline that high-performance GaN JBS can be realized using Mg implantation and high-temperature UHP post-activation anneal.

A comparative study of SiC MOSFETs with and without integrated SBD

A comparative study on SiC MOSFETs is carried out with an emphasis on the design of integrated Schottky barrier diode (SBD) with numerical simulations by Sentaurus TCAD. Compared with the conventional SiC MOSFET (C-MOS) and the conventional SBD-embedded SiC MOSFET (C-MOSBD), the MOSFET (M-MOSBD) features a hybrid doping mesa above the JFET region where a Schottky contact is formed, which exhibits a superior trade-off between the on-state resistance (Rdson) and the reverse transfer capacitance (Crss). Besides, the integrated diode in M-MOSBD renders a better trade-off between OFF-state junction field (ESmax) and forward voltage (VF) when compared to C-MOSBD and the conventional junction barrier Schottky diode (JBS), i.e., the external SBD of C-MOS. In the double pulse test simulation, C-MOS exhibited the largest switch loss followed by C-MOSBD, and M-MOSBD is the smallest. Therefore, in power switching applications where reverse conduction is required, M-MOSBD greatly reduces the chip area while presenting better characteristics.

Design optimization of high breakdown voltage vertical GaN junction barrier Schottky diode with high-K/low-K compound dielectric structure

A vertical junction barrier Schottky diode with a high-K/low-K compound dielectric structure is proposed and optimized to achieve a high breakdown voltage (BV). There is a discontinuity of the electric field at the interface of high-K and low-K layers due to the different dielectric constants of high-K and low-K dielectric layers. A new electric field peak is introduced in the n-type drift region of junction barrier Schottky diode (JBS), so the distribution of electric field in JBS becomes more uniform. At the same time, the effect of electric-power line concentration at the p–n junction interface is suppressed due to the effects of the high-K dielectric layer and an enhancement of breakdown voltage can be achieved. Numerical simulations demonstrate that GaN JBS with a specific on-resistance (R on,sp) of 2.07 mΩ⋅cm2 and a BV of 4171 V which is 167% higher than the breakdown voltage of the common structure, resulting in a high figure-of-merit (FOM) of 8.6 GW/cm2, and a low turn-on voltage of 0.6 V.

A SiC-Si Hybrid Module for Direct Matrix Converter With Mitigated Current Spikes

Reliable and affordable ac/ac power conversion plays a key role in supplying various electrical equipment. Among the options available, the direct matrix converter (DMC) outperforms its counterparts (e.g., ac/dc/ac), in terms of lifespan and compactness, due to its omission of fragile and bulky dc-link capacitors. However, most off-the-shelf DMC modules suffer from high input current spikes, which if unresolved can noticeably increase current stresses and lower efficiency. Origin of the spikes and a mechanism for reducing them are hence studied in this article, before developing a low-cost silicon carbide (SiC)-Si hybrid module for implementing DMC reliably and compactly. The developed module consists of 18 Si insulated gate bipolar transistors (IGBTs) and 18 SiC junction barrier Schottky (JBS) diodes connected in a common-collector structure. The improved reverse recovery property of the SiC JBS diodes then permits the hybrid module to operate with mitigated current spikes. To demonstrate, the hybrid module has been fabricated, tested, and compared with two counterparts in terms of their input current spikes and power losses over different output voltages and switching frequencies. Experimental results have proved the expected performances of the hybrid DMC module, which collectively can accelerate large-scale emergence of small all-semiconductor drives for industrial pumps, cooling and refrigeration systems, and others widely needed in developing economies.

Direct barrier evaluation method for SiC devices with junction barrier Schottky structures demonstrated with quasi-continuous spacing variation

Junction barrier Schottky (JBS) structures are extensively used in silicon carbide devices; however, the complex surface composition makes the direct barrier evaluation difficult. To exclude the field-dependent distortion on a barrier for a direct unbiased evaluation in JBS structures, this work proposes a new evaluation method with a physics-based derivation and experimental demonstration, where a batch of JBS diodes are fabricated with a quasi-continuous spacing variation distribution achieved by the spreading etching technique. In addition, a detailed analysis based on the field-dependent barrier is provided. The result illustrates the chain-like activation and its saturation limit with a quantitative estimate in the straggle region. With the capability of the high linearity to exploit the statistical information for analysis stability, the proposed indicator could be a quantitative and versatile reference for designers dealing with nonideal surfaces.

Failure mechanism of 4H-SiC junction barrier Schottky diodes under harsh thermal cycling stress

The concern in the long-term reliability of the SiC power devies is raised lately in power electronic field due to its brief history and limited data. In this work, discrete 1200 V/20A SiC JBS diodes have been intensively investigated by HTRB, HAST, and TCT. 2 % samples have failed in the harsh thermal cycling test, showing that the failure mechanism is attributed to field-oxide cracking. The electrical and physical failure analysis pointed out that a gradual degradation occurred at the termination structure, causing non-recoverable damages and provoking a significant increase in the leakage current. The FIB cut and SEM analysis showed the delamination existence between field oxide layer and silicon carbide layer in the degraded devices. The observed leakage current after the TCT could be well correlated with the formation of the delamination, which created a current leaking path between active and termination region. These findings emphasize the importance of SiO2/SiC interface quality in the long-term highly reliable SiC power devices, and indicate further optimized design of SiO2 passivation layer or other alternative materials is urgently needed to overcome this structural weakness.

(Invited) Breakthrough Avalanche and Short Circuit Robustness in Vertical GaN Power Devices

After decades of relentless efforts, GaN power devices, specifically, the lateral GaN high-electron mobility transistor (HEMT), have been commercialized in the 15-650 V classes. Owing to GaN’s competitive physical properties over Si and SiC for power electronics, GaN HEMTs allow for higher switching frequency and therefore, have already seen wide adoptions in fast chargers, wireless charging, data centers, and electrified transportation. Despite the success of lateral GaN HEMTs, a vertical device structure is usually believed to be more favorable for high-voltage, high-power devices. In the last few years, with the advent and maturity of large-diameter, low-dislocation GaN wafers on freestanding GaN substrates, a new generation of vertical GaN power devices have been developed to extend GaN’s application space beyond 650 V. Very recently, several industrial vertical GaN devices in the voltage classes of 1.2-1.7 kV have been demonstrated, which are close to commercialization.This presentation will review the key advancements in vertical GaN power devices in the past decade, with a focus on the device technologies that are being commercialized, and provide a prospective for research and development in the next decade. The devices to be covered will include two-terminal power rectifiers including the p-n diodes, Schottky barrier diodes, junction barrier Schottky diodes, and trench MIS/MOS barrier Schottky diodes. The transistors will include the trench and planar MOSFETs, current-aperture vertical electron transistors, fin-channel MOSFETs, and fin-channel JFETs. Particular emphasis will be on large-area rectifiers and transistors with a device performance superior to similarly-rated Si and SiC transistors. The newly demonstrated avalanche and short-circuit robustness in vertical GaN devices, which are lacking in lateral GaN HEMTs, as well as their underlying device physics, will also be introduced. The presentation will be concluded by a discussion of current challenges and future application spaces of vertical GaN devices, as well as emerging vertical GaN devices (e.g., superjunction) under development.

Isotopic Enriched and Natural SiC Junction Barrier Schottky Diodes Under Heavy Ion Irradiation

The radiation tolerance of isotopic enriched and natural silicon carbide junction barrier Schottky diodes are compared under heavy ion irradiation. Both types of devices experience leakage current degradation as well as single-event burnout events. The results were comparable, although the data may indicate a marginally lower thresholds for the isotopic enriched devices at lower linear energy transfer (LET). Slightly higher reverse bias threshold values for leakage current degradation were also observed compared to previously published work.

Design Space of GaN Vertical Trench Junction Barrier Schottky Diodes: Comprehensive Study and Analytical Modeling

We report gallium nitride (GaN) vertical trench junction barrier Schottky (TJBS) diodes and systematically analyzed the effects of the key design parameters on the reverse and forward characteristics of the devices. By taking advantage of the shielding effects from both the trenches and pn junctions in the TJBS structure, the high electric field at the Schottky contact region can be effectively suppressed. We found that the doping concentration, thickness, and spacing of p-GaN, as well as the depth and angle of the trench sidewalls are closely associated with the electric field distribution and the reverse characteristics of the TJBS diodes. With an optimal set of design parameters, the local electric field crowding at either the corner of the trench or the edge of the p-GaN can also be alleviated, resulting in a boosted breakdown voltage of up to 1250 V in the TJBS diodes. In addition, an analytical model was developed to explore the physical mechanism behind the forward conduction behaviors. We believe that the results can provide a systematical design strategy for the development of low-loss, high-voltage, and high-power GaN power diodes towards an efficient power system.

Reduced On-Resistance and Improved 4H-SiC Junction Barrier Schottky Diodes Performance by Laser Annealing on C-Face Ohmic Regions in Thin Structures

In this study, we investigated the characteristics of the n-type Ni/SiC ohmic contact using the laser annealing process on thin wafers. The electrical behavior of the ohmic contacts was tested in 4H-SiC JBS diode devices. As a result, a wafer thickness of 100 μm in the 4H-SiC JBS diode achieved a forward voltage of 1.33 V at 20 A with a laser annealing process using Ni silicide. Using a laser annealing process on a wafer thickness of 100 μm, an on-resistance decrease of almost 22% was demonstrated. Based on our experimental results, we suggest an alternative laser annealing fabrication scheme to obtain low on-resistance SiC power devices with thin structures after SiC grinding.

A SiC sidewall enhanced trench JBS diode with improved forward performance

A new high-performance sidewall enhanced trench junction barrier Schottky (SET-JBS) diode is proposed in this article. In the proposed SET-JBS diode, in addition to the Schottky contact on the top anode, the sidewall of the trenches also introduces Schottky contacts, which not only increases the Schottky contact area, but also weakens the junction field-effect transistor effect of the device, resulting in a high forward current density and a low specific on-resistance (R on,sp) with a small increase in reverse leakage current (J L). Simulation results show that the R on,sp of the proposed SET-JBS diode is reduced by 21.6%–46.7% with less than an order of magnitude increase in leakage current compared with that of the conventional trench JBS (T-JBS) diode when the trench distance is from 2.1 μm to 1.2 μm at the 2 μm trench depth. And the SET-JBS diode also performs better than the trench MOS barrier Schottky (TMBS) diode when comprehensively considered the R on,sp and J L. And the figure of merit and the trade-off relationship between the R on,sp and the breakdown voltage of the proposed SET-JBS both are better than those of the conventional T-JBS diode and TMBS diode. The forward I–V analytical model of the SET-JBS is also proposed, which is in good agreement with the simulation results. All the simulation results indicate that the proposed SET-JBS diode has promising potential in power electronics applications.

The Research on Screening Method to Reduce Chip Test Escapes by Using Multi-Correlation Analysis of Parameters

Chip test escapes can pass the complete test procedure but fail prematurely in system applications. Statistical testing methods can screen chip test escapes by analyzing test data without additional physical measurements. This paper proposes a screening method to reduce chip test escapes using multi-correlation analysis of parameters. This method takes the strength of locational correlation or structural correlation as criterion information. The main steps of the method are as follows: first, quantifying the strength of locational correlation or structural correlation of the chip parameters, then verifying the statistical distribution of the characterization and setting the screening limit, and finally, screening the chip test escapes. Silicon carbide junction barrier Schottky diode (JBS) measurement data are used to verify the method. The results show that when the location information of the chip on the wafer is known, the screening effect based on locational correlation is significantly better than the method specified in AEC Q101. Without additional physical measurements, screening methods based on structural correlation can further identify the remaining chip test escapes in single-parameter screening. This screening method can be used to supplement the existing measurement technology to reduce the cost of packaging, testing, and aging testing.

The Optimization of 3.3 kV 4H-SiC JBS Diodes

The article reports a comprehensive study optimizing the OFF- and ON-state characteristics of 3.3 kV junction barrier Schottky (JBS) diodes made using nickel, titanium, and molybdenum contact metals. In this design, the same implants used in the optimized termination region are used to form the P-regions in the JBS active area. The width and spacing of the P-regions are varied to optimize both the ON- and OFF-state of the device. All the diodes tested displayed high blocking voltages and ideal turn-on characteristics up to the rated current of 2 A. However, the leakage current and the Schottky barrier height (SBH) were found to scale with the ratio of Schottky to p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions. Full Schottkys, without p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions, and those with very wide Schottky regions had the lowest SBH (1.61 eV for Ni, 1.11 eV for Mo, and 0.87 eV for Ti) and the highest leakage. Those diodes with the lowest Schottky openings of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 ~\mu \text{m}$ </tex-math></inline-formula> had the lowest OFF-state leakage, but they suffered severe pinching from the surrounding p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> regions, increasing their SBH. The best performing JBS diodes were Ni and Mo devices with the narrowest pitch, with the p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> implants/Schottky regions both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 ~\mu \text{m}$ </tex-math></inline-formula> wide. These offered the best balanced device design, with excellent OFF-state performance, while the Schottky ratio guaranteed a relatively low forward voltage drop.