The Research on Screening Method to Reduce Chip Test Escapes by Using Multi-Correlation Analysis of Parameters

Abstract

Chip test escapes can pass the complete test procedure but fail prematurely in system applications. Statistical testing methods can screen chip test escapes by analyzing test data without additional physical measurements. This paper proposes a screening method to reduce chip test escapes using multi-correlation analysis of parameters. This method takes the strength of locational correlation or structural correlation as criterion information. The main steps of the method are as follows: first, quantifying the strength of locational correlation or structural correlation of the chip parameters, then verifying the statistical distribution of the characterization and setting the screening limit, and finally, screening the chip test escapes. Silicon carbide junction barrier Schottky diode (JBS) measurement data are used to verify the method. The results show that when the location information of the chip on the wafer is known, the screening effect based on locational correlation is significantly better than the method specified in AEC Q101. Without additional physical measurements, screening methods based on structural correlation can further identify the remaining chip test escapes in single-parameter screening. This screening method can be used to supplement the existing measurement technology to reduce the cost of packaging, testing, and aging testing.