Inversion Layer Capacitance Research Articles

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Modeling of inversion layer capacitance of III-V double gate MOSFETs using a neural network-based regression technique

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET

The paper proposes analytical model for Gate-All-Around Metal Oxide Semiconductor Field Effect Transistor (GAA-MOSFET) for germanium channel including quantum mechanical effects. It is achieved by solving coupled Schrodinger-Poisson’s equation using variational approach. The proposed model takes quantum confinement effects to obtain charge centroid and inversion charge model. By using these models the quantum version of inversion layer capacitance, inversion charge distribution function and Drain current expressions are modelled and the performance evaluation of the developed model is compared with Silicon channel GAA-MOSFET. Analytically modelled expressions are verified by comparing the model with simulation results.

Physical investigation of gate capacitance in In0.53Ga0.47As/In0.52Al0.48As quantum-well metal-oxide-semiconductor field-effect-transistors

In this paper, we aim to decompose gate capacitance components in InGaAs/InAlAs quantum-well (QW) metal-oxide-semiconductor field-effect-transistors (MOSFETs), in an effort to physically investigate their gate capacitance (Cg). First, we verified their validity with 1-D simulation and experimental Cg data in various types of InGaAs/InAlAs QW MOSFETs with different channel thickness (tch). Both quantum capacitance (CQ) and centroid capacitance (Ccent) were highly relevant to total gate capacitance (Cg) of the InGaAs/InAlAs QW MOSFETs. Second, the total Cg did not saturate at a strong inversion regime. This is a consequence of the second subband inversion layer capacitance (Cinv_2) and, more importantly, its increase with VG. Lastly, we studied the role of channel thickness (tch) scaling, which helps to increase the total gate capacitance by enhancing both CQ and Ccent.

Compact Modeling of Qunatum Effects in Undoped Long- Channel Cylindrical Surrounding-Gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for cylindrical surrounding-gate or gate-all-around metal oxide semiconductor field effect transistors (MOSFETs). By extracting some constants parameter from the self-consistent Schrodinger and Poisson equations, two physical parameters, threshold voltage shift and inversion layer centroid, are expressed as closed form function of device radius and charge density. The quantum version of inversion charge density is obtained by incorporating of those parameters into the classical procedure as modifications for gate work function and inversion layer capacitance. The model represented here has been able to reproduce simulation data obtained from self-consistent calculation. The calculated results show that the model fits well with the self-consistent calculation.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm–5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (Vth) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φc) saturates to Φc(sat), and analyze the effects of oxide thickness (tox) and substrate doping (NA) variations on Vth. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed Vth definition, electrically corresponds to a condition where the inversion layer capacitance (Cinv) is equal to the oxide capacitance (Cox) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria Cinv=Cox is proposed to compute Φc(sat), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (“x”) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film.

The low frequency behaviour in high frequency capacitance–voltage characteristics due to contribution of band-to-band tunnelling and generation–recombination in Hg 0.75Cd 0.25Te MIS capacitors

Hg 1− x Cd x Te Metal–Insulator–Semiconductor (MIS) capacitors were studied both experimentally and theoretically to investigate the capacitance contributions due to band-to-band (btb) tunnelling and generation–recombination (gr) of carriers to inversion layer capacitance. A good fit to the data has been obtained by including the btb contributions rather than gr contributions.

Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime

We investigate the determining mechanisms of the inversion-layer capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> is experimentally evaluated.

Physical Origin of Drive Current Enhancement in Ultrathin Ge-on-Insulator n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Full Ballistic Transport

Drive current (Isat) of ultrathin germanium-on-insulator (GOI) n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) under full ballistic transport is theoretically investigated for (100)-, (110)-, and (111)-oriented Ge surfaces. The physical origin of the current drive enhancement associated with thinning GOI films for each surface orientation is clarified from the viewpoints of injection velocity (vinj) and inversion-layer capacitance (Cinv). It is found that vinj on (111) is significantly enhanced with decreasing the GOI thickness (TGOI), while no enhancement is observed for (100). This increase in vinj on (111) originates in the increase in the electron occupancy of the lowest subband due to the size effect of ultrathin GOI films. On the other hand, Cinv on (111) slightly decreases with a decrease in TGOI, because of the stronger influence of Cinv due to the density-of-states. In contrast, Cinv on (100) significantly increases with a decrease in TGOI, because of the increase in Cinv due to the inversion-layer thickness, determined by the GOI physical thickness. The (110) GOI surface is found to have intermediate characters between (100) and (111). When Isat is compared under a given gate voltage, the optimum surface orientation is dependent on TGOI and gate oxide thickness (Tox), because of the trade-off relationship in the effective mass between vinj and Cinv. In bulk Ge and GOI with TGOI thicker than around 5 nm, (111) and (110) surfaces can provide the identical and maximum Isat independent of Tox, which is attributed to the higher vinj. In GOI with TGOI thinner than around 5 nm, Isat is higher in the order of (111), (110), and (100) for Tox thicker than around 1 nm, while in the order of (110), (100), and (111) in TGOI thinner than around 1 nm, because of the lowest Cinv on (111). Here, the transition Tox is dependent on TGOI. As a consequence, we can conclude that, in a realistic choice of TGOI and Tox, (111) and (110) surfaces can yield higher Isat in GOI n-MOSFETs.

Characterization of Inversion-Layer Capacitance of Electrons in High- $k$/Metal Gate Stacks

The inversion-layer capacitance Cinv of electrons in high-k/metal gate stacks (HKMGs) is studied theoretically and experimentally from the viewpoint of the penetration of electrons into the dielectrics. The numerical calculation of Cinv in the dielectric/substrate bilayer structure has clarified the influence of penetration on Cinv . Cinv in an HKMG is evaluated experimentally and is compared with the computational predictions in terms of the dependence on the dielectric boundary and the silicon crystal orientation. The consistency of the experiment and the calculation is the first evidence for the considerable modulation of Cinv due to penetration in the actual HKMG. Moreover, the dependence of Cinv on substrate biasing is investigated. The detailed analysis of Cinv in the system where the confinement of the inversion layer is intentionally changed has led to a further understanding of Cinv determined by penetration.

Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

Inversion charge (Qi) and oxide capacitance (Cox') of undoped (or lightly doped) or doped double-gate (DG) and surrounding-gate (SG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with long channel were analytically modeled by considering inversion-layer capacitance (Ci) in linear region. The Qi model of DG and SG MOSFETs was derived with a closed-form as a function of gate bias (VGS), threshold voltage (Vth), and body structure factor (n) using one-dimensional (1D) Poisson's equation considering the mobile carrier. The n which reflects silicon body structure effect is 1 for DG MOSFETs and less than 1 for SG MOSFETs irrespective of channel doping (Nb). From the derived Qi model considering the Ci effect, the Cox' was modeled and applied to the ID–VGS model of undoped or doped DG and SG MOSFETs in linear region. The compact current model using our proposed Cox' predicted more accurately the on-current behavior than that with the oxide capacitance (Cox) in linear region.

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C–V and I–V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.

Attofarad resolution capacitance–voltage measurement of nanometer scale field effecttransistors utilizing ambient noise

A high resolution capacitance–voltage (C–V) characterization technique, enabling direct measurement of electronic properties at thenanoscale in devices such as nanowire field effect transistors (FETs) through the use ofrandom fluctuations, is described. The minimum noise level required for achieving sub-aF (10−18 F) resolution, the leveraging of stochastic resonance, and the effect ofhigher levels of noise are illustrated through simulations. The non-linearΔCgate−source/drain–Vgate response of FETs is utilized to determine the inversion layer capacitance (Cinv) and carrier mobility. The technique is demonstrated by extracting the carrierconcentration and effective electron mobility in a nanoscale Si FET withCinv = 60 aF.

Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel

The current behaviors of fully depleted (FD) symmetric double-gate (DG) metal–oxide–semiconductor field effect transistors (MOSFETs) with doped short-channel were parametrically modeled with the simple closed-form in all operational regions. In the diffusion current model, a physical parameter DG as a function of gate bias (VGS), drain bias (VDS), silicon body width (WB), channel length (L), and channel doping concentration (Nb) was introduced to consider the VGS dependence. Also, the subthreshold slope (SS) of DG MOSFETs with doped channel was modeled accurately with DG. DD which is dependent on VDS was introduced to consider the drain-induced barrier lowering (DIBL) in the diffusion current model. After the strong inversion, the drift current of doped DG MOSFETs was modeled by considering inversion-layer capacitance based on charge-sheet approximation. The channel length modulation by VDS was considered for accuracy in the current modeling of DG MOSFETs with doped short-channel. Our simple compact models predicted accurately DC characteristics of the devices with the channel length to 20 nm and shown good agreement with two-dimensional (2D) simulation.

First-principles study on inversion layer properties of double-gate atomically thin silicon channels

The inversion layer properties of double-gate atomically thin silicon channels are studied based on the first-principles enforced Fermi energy difference method. The calculated results indicate that the atomic-scale thickness of the channel significantly affects the inversion layer capacitance as well as the inversion layer carrier properties. They also indicate that the first-principles approach is essential and practical for studying the device physics of the field effect transistors with nanometer-scale channels.

Si–SiO2 interface band‐gap transition – effects on MOS inversion layer

AbstractDensity functional theory simulation results of the atomic structure at the Si–SiO2 interface implies a non‐abrupt transition of the band‐gap within the oxide. The depth of the transition, 2–6 Å, is comparable to the approximately 1 nm oxide thickness in nano‐CMOS devices, and is expected to affect their characteristics. Using hierarchical simulation approach, we combine for the first time ab‐initio density functional theory simulations of the interface, with self‐consistent Poisson–Schrödinger one‐dimensional device simulations, and estimate the impact of interface band‐gap transition on the inversion layer quantisation, capacitance, and tunnelling characteristics of a metal–oxide–semiconductor structure. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Influence of Bandstructure and Channel Structure on the Inversion Layer Capacitance of Silicon and GaAs MOSFETs

The influence of MOSFET channel material and channel structure on the inversion layer capacitance is examined. It is well known that the inversion layer capacitance depends strongly on the bandstructure of the channel, but we show that it also depends very strongly on the structure of the channel (e.g., bulk vs. ultrathin body, and the thickness of the body). These results provide some general insights into the channel material and structure tradeoffs that control the inversion layer capacitance-an increasingly important consideration as electrical oxide thicknesses continue to decrease and as new channel materials are considered.

Simulation of Capacitance-Voltage characteristics of Ultra-thin Metal-Oxide-Semiconductor Structures with Embedded Nanocrystals

AbstractThis paper presents an approach to model quantum mechanical effects in solid-state devices such as Metal Oxide Semiconductor (MOS) capacitor with and without nanocrystal in the oxide at the device simulation level. This quantum-mechanical model is developed to understand finite inversion layer width and threshold voltage shift. It allows a consistent determination of the physical oxide thickness based on an agreement between the measured and modeled C-V curves. However, as for thinner oxides finite inversion layer width effects become more severe, quantum-mechanical model predicts higher threshold voltage than the classical model. The inversion-layer charge density and MOS capacitance in multidimensional MOS structures are simulated with various substrate doping profiles and gate bias voltages. The effectiveness of the QM correct method for modeling quantum effects in ultrathin oxide MOS structures is also investigated. The CV characteristic is used as a tool to compare results of the QM correction with that of the Schrödinger–Poisson (SP) solution and Classical solution The variation of (different parameters) for various doping profiles at different gate voltages is investigated.

Semiconducting Behavior of Epoxy Resin/Carbon Steel in Sulfuric Acid Solution

Semiconductor behavior of epoxy resin coated on carbon steel immersed in 0.5 mol·L-1 sulfuric acid aqueous solution during its degradation was investigated. Potential (U)-capacitance (C) measurement and Mott-Schottky analysis technology were utilized to understand the coat′s conduction mechanism during its degradation in the electrolyte. The epoxy resin film was still an insulator in the initial immersion stage (10 min), but its outer layer (the side that contacts with solution) gradually changed into n type semiconductor due to the corrosion with growing immersion time. Charge carrier density of this semiconductor film increased by degrees with extension of immersion time from 1010 cm-3 at 7 h to 1012 cm-3 at 48 h approximately. Between 7 h and 48 h, the organic film had not entirely transformed into semiconductor but only the outer side, and the inner was still insulator. Therefore, an MIS structure (metal-insulator-semiconductor) was generated. The result indicated that this MIS structure was in inversion state between -0.5 V and 0.5 V, and carrier charges were electron holes in inversion layer. The measured space-charge capacitance was series capacitance of inversion layer capacitance and depletion layer capacitance at relatively low frequency. The capacitance value decreased with growing polarization potential. The measured capacitance at relatively high frequency was only the depletion layer capacitance and remained constant in the total scanning potential region. An anodic drift occurred about the C-U characteristic curve of the MIS structure.

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.