Gate Capacitance Reduction Due to the Inversion Layer in High- $k$/Metal Gate Stacks Within a Subnanometer EOT Regime

Abstract

We investigate the determining mechanisms of the inversion-layer capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> is experimentally evaluated.