Inversion Channel Mobility Research Articles

Reduced electric field in junctionless transistors

The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.

Improved Inversion Channel Mobility in Si-face 4H-SiC MOSFETs by Phosphorus Incorporation Technique

AbstractWe propose a new technique to fabricate 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) with high inversion channel mobility. P atoms were incorporated into the SiO2/4H-SiC(0001) interface by post-oxidation annealing using phosphoryl chloride (POCl3). The interface state density at 0.2 eV from the conduction band edge was reduced to less than 1 × 1011 cm−2eV−1 by the POCl3 annealing at 1000 °C. The peak field-effect mobility of 4H-SiC MOSFETs on (0001) Si-face processed with POCl3 annealing at 1000 °C was approximately 90 cm2/Vs. The high channel mobility is attributed to the reduced interface state density near the conduction band edge.

GaN metal-oxide-semiconductor field-effect transistor inversion channel mobility modeling

Lateral n-channel enhancement-mode GaN metal-oxide-semiconductor (MOS) field-effect transistors and lateral capacitors have been fabricated on a p-type epi-GaN substrate semiconductor and electrically characterized at different temperatures. A clear positive behavior of the inversion channel mobility with temperature has been obtained. A physics-based model on the inversion charge and charge trapped in interface states characteristics has been used to investigate the temperature dependence of the inversion MOS channel mobility. The field-effect mobility increase with temperature is due to an increase in the inversion charge and a reduction in the trapped charge for a given voltage gate. Then, for larger gate bias and/or higher temperatures, surface roughness effects become relevant. The good fitting of the model with the experimental data leads us to consider that the high density of charged acceptor interface traps together with a large interface roughness modulates the channel mobility due to scattering of free carriers in the inversion layer. A closed form expression for the experimental inversion MOS channel mobility is proposed.

Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high- k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO 2. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm 2/Vs have been found for GdSiO.

Effect of Graphite Cap for Implant Activation on Inversion Channel Mobility in 4H-SiC MOSFETs

The effects of using a graphite capping layer during implant activation anneal on the performance of 4H-SiC MOSFETs has been evaluated. Two sets of samples, one with the graphite cap and another without, with a gate oxide process consisting of a low-temperature deposited oxide followed by NO anneal at 1175°C for 2hrs were used for characterization. Various device parameters, particularly threshold voltage, subthreshold slope, field-effect mobility, inversion sheet carrier concentration and Hall mobility have been extracted for the two processes.

Atomistic Scale Modeling and Analysis of Sodium Enhanced Oxidation of Silicon Carbide

We explain the phenomenon of sodium enhanced oxidation (SEO) using computational techniques, and analyze a set of probable hypotheses, which can elucidate the observation of high inversion channel mobility achieved with SEO. The ability of the Na to screen the interface traps, reduce carbon cluster type of defect formation, and enhance the oxidation rate can be explained using these calculations. We observe an increased availability of electrons near the interface in the presence of Na. The sodium atom also helps in breaking the intramolecular oxygen bond. The electronic and atomic structure of the interface cluster, and electric field computations showed that the carbon cluster formed at the oxide side of the interface could be screened by the Na ion.

Improvement of Channel Mobility in Inversion-Type n-Channel GaN Metal–Oxide–Semiconductor Field-Effect Transistor by High-Temperature Annealing

Inversion- and depletion-type GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) were fabricated on p- and n--type GaN epitaxial layers, respectively, grown on n+-type on-axis 4H-SiC(0001) substrates. After gate SiO2 was deposited by plasma-enhanced chemical vapor deposition at 350 °C, high-temperature annealing in N2 was carried out to modify the interface. The channel mobility was enhanced with increasing annealing temperature. The device annealed in N2 at 1100 °C after SiO2 deposition showed an inversion channel mobility of 108 cm2·V-1·s-1 at a gate voltage of 15 V. The authors also fabricated MOS capacitors on n--type GaN and characterized the interface state density at the SiO2/GaN interface from capacitance–voltage measurements using the Terman method, of which density was estimated to be in the range of (6–10)×1011 cm-2·eV-1 at an energy level of 0.2 eV below the conduction band edge. The interface state density tended to decrease with increasing annealing temperature, resulting in the improvement of the channel mobility.

Effect of Gate Wet Reoxidation on Reliability and Channel Mobility of Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on 4H-SiC(000-1)

The channel mobility and oxide reliability of metal-oxide-semiconductor field-effect transistors (MOSFETs) on 4H-SiC (0001) carbon face were investigated. The gate oxide was fabricated by using dry-oxidized film followed by pyrogenic reoxidation annealing (ROA). Significant improvements in the oxide reliability were observed by time-dependent dielectric breakdown (TDDB) measurement. Furthermore, the field-effect inversion channel mobility (μFE) of MOSFETs fabricated by using pyrogenic ROA was as high as that of conventional 4H-SiC (0001) MOSFETs having the pyrogenic-oxidized gate oxide. It is suggested that the pyrogenic ROA of dry oxide as a method of gate oxide fabrication satisfies both channel mobility and oxide reliability on 4H-SiC (0001) carbon-face MOSFETs.

Sodium Enhanced Oxidation of Si-Face 4H-SiC: A Method to Remove Near Interface Traps

We demonstrate how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2/4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1-10 cm2/Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these nearinterface traps resulting in high inversion channel mobility of 150 cm2/Vs in such transistors. Sodium can be incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during formation of the SiC/SiO2 interface.

Realization of Low On-Resistance 4H-SiC Power MOSFETs by Using Retrograde Profile in P-Body

Inversion-type 4H-SiC power MOSFETs using p-body implanted with retrograde profiles have been fabricated. The Al concentration at the p-body surface (Nas) is varied in the range from 5×1015 to 2×1018 cm-3. The MOSFETs show normally-off characteristics. While the Ron is 3 cm2 at Eox = (Vg-Vth)/dox ≅ 3 MV/cm for the MOSFET with the Nas of 2×1018 cm-3, the Ron is reduced by a decrease in the Nas and 26 mcm2 is attained for the device with the Nas of 5×1015 cm-3. The inversion channel mobility and threshold voltage are improved with a decrease in the Nas. By modifying the structural parameter of the MOSFET, a still smaller Ron of 7 mcm2 is achieved with a blocking voltage of 1.3 kV.

Increased Channel Mobility in 4H-SiC UMOSFETs Using On-Axis Substrates

The achievement of high channel mobility in UMOSFETs by utilizing on-axis substrates is reported. UMOSFETs were fabricated on commercially available C-face 4H-SiC on-axis substrates. The MOS channels were formed on the single side of the trench sidewalls to be (1120), (1120), (1100), and (1100). By using on-axis substrates, channel mobility on (1120) was greatly improved to 66cm 2 /Vs, which is similar value (71cm 2 /Vs) on (1120). These values are the highest inversion channel mobility in 4H-SiC UMOSFETs ever reported. These results suggest that the channel plane should be close to the crystallographically accurate {1120} to increase channel mobility.

A strong reduction in the density of near-interface traps at the SiO2∕4H-SiC interface by sodium enhanced oxidation

This paper demonstrates how sodium enhanced oxidation of Si face 4H-SiC results in removal of near-interface traps at the SiO2∕4H-SiC interface. These detrimental traps have energy levels close to the SiC conduction band edge and are responsible for low electron inversion channel mobilities (1–10cm2∕Vs) in Si face 4H-SiC metal-oxide-semiconductor field effect transistors. The presence of sodium during oxidation increases the oxidation rate and suppresses formation of these near-interface traps resulting in high inversion channel mobility of 150cm2∕Vs in such transistors. Sodium is incorporated by using carrier boats made of sintered alumina during oxidation or by deliberate sodium contamination of the oxide during the formation of the SiC∕SiO2 interface.

Comparison between oxidation processes used to obtain the high inversion channel mobility in 4H-SiC MOSFETs

In this work two oxidation methods aimed at improving the silicon face 4H-SiC/SiO2 interface are compared. One is an oxidation in N2O performed in a quartz tube using quartz sample holders and the other is a dry oxidation performed in an alumina tube using alumina sample holders. In n-type metal oxide semiconductor (MOS) capacitors the interface state density near the SiC conduction band edge is estimated using capacitance–voltage (C–V) and thermal dielectric relaxation current (TDRC) measurements. N-channel metal oxide semiconductor field effect transistors (MOSFETs) are characterized by current–voltage (I–V) techniques and the inversion channel mobility is extracted. It is shown that the high inversion channel mobility (154 cm2 V−1 s−1) seen in samples oxidized using alumina correlates with a low interface trap density (3.6 × 1011 cm−2). In the case of N2O oxidation the mobility is lower (24 cm2 V−1 s−1) and the interface trap density is higher (1.6 × 1012 cm−2). Room temperature C–V measurements are of limited use when studying traps near the conduction band edge in MOS structures while the TDRC measurement technique gives a better estimate of their density.

High Inversion Channel Mobility of 4H-SiC MOSFETs Fabricated on C(000-1) Epitaxial Substrate with Vicinal (Below 1º) Off-Angle

SiC power MOSFETs are expected to be normally-off type fast switching devices. The on-resistance of SiC power MOSFETs is much higher than the value predicted from the physical properties of SiC. This is caused by the low channel mobility due to high interface state density (Dit). We have already reported that 4H-SiC MOSFETs on the C(0001 _ ) face had higher inversion-channel mobility. However, there is the SiO2/SiC interface roughness problem in SiC MOSFETs. There are many steps at the SiO2/SiC interface because a high off-angle is necessary for SiC epitaxial growth. These steps might make SiO2/SiC interfaces rough, which leads to reduction of channel mobility. In this work, we have investigated the effect of the SiO2/SiC interface roughness caused by the off-angle on the inversion channel mobility of 4H-SiC MOSFETs fabricated on the C(0001 _ ) face. The inversion-channel mobility of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the vicinal off-angle(0.8°) is higher than that of MOSFETs fabricated on the 4H-SiC C(0001 _ ) face substrate with the 8° off-angle. Reduction of the off-angle is very useful for improvement of channel mobility. A C(0001 _ ) epitaxial substrate with the vicinal off-angle would be suitable for SiC DMOSFETs.

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO 2 barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures. Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO 2 system causes the barrier height between SiC and SiO 2 to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO 2. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required. In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC. Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.

High current capability of 3C-SiC vertical DMOSFETs

Vertical power DMOSFETs in 3C-SiC, ranging in size from a single-cell to 3 × 3 mm 2 containing 12,000 hexagonal cells, were developed for the first time. Both the drain and leakage currents scale linearly with device size up to a 1 × 1 mm 2 device containing 976 cells. An inversion channel mobility of 40 cm 2/V · s and interface state density of 5 × 10 12 to 1 × 10 13 cm −2 eV −1 were obtained. A fabricated DMOSFET with a gate length of 2 μm had a low specific on-resistance of 5.6 mΩ · cm 2 for a single-cell device. A current density of 1220 A/cm 2 for a single-cell device, and 380 A/cm 2 for a 102-cell device were demonstrated. A high current capability of 41 to 132 A at 600 V can be extrapolated for a 3 × 3 mm 2 chip.

Effects of chlorine on interfacial properties and reliability of SiO2 grown on 6H-SiC

A new process of oxidizing 6H-SiC in dry O2+trichloroethylene (TCE) is used to incorporate chlorine in SiO2. The interface quality and the reliability of 6H-SiC MOS capacitors with gate dielectrics prepared by the process are examined. As compared to the conventional dry O2 oxidation, the O2+TCE oxidation results in lower interface-state density, reduced oxide-charge density and enhanced reliability. This could be attributed to the passivation effects of Cl2 and HCl on the structural defects at/near the SiC/SiO2 interface, and also their gettering effects on ion contamination. Moreover, post-oxidation NO annealing, especially in a wet ambient, can further decrease the interface-state density and the oxide-charge density. Lastly, an increased oxidation rate induced by TCE is observed and should be useful for reducing the normally high thermal budget of oxide growth. All these are very attractive for fabricating SiC MOSFETs with high inversion-channel mobility and high hot-carrier reliability.

Investigation of Degradation of Inversion Channel Mobility of SiC MOSFET due to the Increase of Channel Doping

This paper reports on the degradation of inversion channel mobility of SiC MOSFET caused by the increase of channel doping. SiC MOSFETs were fabricated on three wafers, the doping concentrations of the epitaxial layer of which were 16 10 2× cm-3 (sample A), 17 10 2× cm-3 (sample B) and 17 10 4× cm-3 (sample C). The field effect mobility sharply decreases as the doping concentration increases. Hall mobility measurements have been done to investigate the degradation of the mobility due to doping. The measurement of sample A shows that, as a consequence of the decrease of the free carrier density due to MOS interface traps, the Hall mobility is as much as a factor of ten higher than the field effect mobility. In contrast, in regard to the measurement of sample B and sample C, we encountered unstable Hall voltage and could not obtain reproducible results. This implies that such high-density traps are generated that a channel disappears in the higher-doping samples.

High Field Effect Mobility in 6H-SiC MOSFET with Gate Oxides Grown in Alumina Environment

Lateral inversion channel metal-oxide-semiconductor field-effect transistors (MOSFETs) were manufactured on 6H-SiC and two gate oxidation recipes were compared. In one case the gate oxide was grown in N2O using quartz environment. The resulting peak field-effect mobility was µFE=43 cm2/Vs. In the other case the gate oxide was grown in oxygen using alumina environment and the resulting peak field-effect mobility was µFE=130 cm2/Vs. Oxidizing in an environment made from sintered alumina introduces contaminants into the oxide that effect the oxidation in several^ways. The oxidation rate is increased and the resulting SiC/SiO2 interface allows higher inversion channel mobility.

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.