Intrinsic Device Research Articles

Electrical Characterization of the Self-Heating Effect in Oxide Semiconductor Thin-Film Transistors Using Pulse-Based Measurements

The self-heating effect (SHE) in top-gate In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) was examined systematically using short electrical pulse measurement methods. The temperature dependence of the pulse measurements of IGZO TFTs revealed a significant increase in temperature during the measurements, suggesting that conventional measurements can overestimate the device performance significantly. The effective temperature was introduced and extracted for IGZO TFTs at various heating powers and ambient temperatures. The short sampling time was determined to be a key in characterizing the intrinsic device properties that are not influenced by the SHE. The cooling behavior after self-heating was also examined using multipulse measurements. Because heating and cooling are significant even in a very short time, it is essential to consider the operation condition of the devices when characterizing TFTs to estimate the precise performance and reliability in a real operation.

Improving Performances of In-Plane Transition-Metal Dichalcogenide Schottky Barrier Field-Effect Transistors.

Monolayer Schottky barrier (SB) field-effect transistors based on the in-plane heterojunction of 1T/1T'-phase (metallic) and 2H-phase (semiconducting) transition-metal dichalcogenides (TMDs) have been proposed following the recent experimental synthesis of such devices. By using density functional theory and ab initio simulations, intrinsic device performance, sub-10 nm scaling, and performance boosting of MoSe2, MoTe2, WSe2, and WTe2, SB field-effect transistors are systematically investigated. We find that the Schottky barrier heights (SBHs) of these in-plane 1T(1T')/2H contacts are proportional to their band gaps: the bigger band gap corresponds to bigger SBH. For four TMDs, the SBH of 1T/2H contact is always smaller than that of 1T'/2H contact. The WTe2 SB field-effect transistor can provide the best performance and satisfy the requirement of the high-performance transistor outlined by the International Technology Roadmap for Semiconductors down to a 6 nm gate length. In addition, the replacement of suitable 1T-TMD on the source/drain regions can modulate conduction band SB, leading to the 8.8 nm WSe2 SB field-effect transistor also satisfying the requirement. Moreover, the introduction of the underlap can increase the effective channel length and reduce the coupling between the source/drain and the channel, leading to the 5.1 nm WTe2 SB field-effect transistor also satisfying the International Technology Roadmap for Semiconductors high-performance requirement. The underlying physical mechanisms are discussed, and it is concluded that the in-plane SB engineering is the key point to optimize such two-dimensional devices.

Impact of Synaptic Device Variations on Pattern Recognition Accuracy in a Hardware Neural Network

Neuromorphic systems (hardware neural networks) derive inspiration from biological neural systems and are expected to be a computing breakthrough beyond conventional von Neumann architecture. Interestingly, in neuromorphic systems, the processing and storing of information can be performed simultaneously by modulating the connection strength of a synaptic device (i.e., synaptic weight). Previously investigated synaptic devices can emulate the functionality of biological synapses successfully by utilizing various nano-electronic phenomena; however, the impact of intrinsic synaptic device variability on the system performance has not yet been studied. Here, we perform a device-to-system level simulation of different synaptic device variation parameters in a designed neuromorphic system that has the potential for unsupervised learning and pattern recognition. The effects of variations in parameters such as the weight modulation nonlinearity (NL), the minimum-maximum weight (Gmin and Gmax), and the weight update margin (ΔG) on the pattern recognition accuracy are analyzed quantitatively. These simulation results can provide guidelines for the continued design and optimization of a synaptic device for realizing a functional large-scale neuromorphic computing system.

Combined scanning probe electronic and thermal characterization of an indium arsenide nanowire.

As electronic devices are downsized, physical processes at the interface to electrodes may dominate and limit device performance. A crucial step towards device optimization is being able to separate such contact effects from intrinsic device properties. Likewise, an increased local temperature due to Joule heating at contacts and the formation of hot spots may put limits on device integration. Therefore, being able to observe profiles of both electronic and thermal device properties at the nanoscale is important. Here, we show measurements by scanning thermal and Kelvin probe force microscopy of the same 60 nm diameter indium arsenide nanowire in operation. The observed temperature along the wire is substantially elevated near the contacts and deviates from the bell-shaped temperature profile one would expect from homogeneous heating. Voltage profiles acquired by Kelvin probe force microscopy not only allow us to determine the electrical nanowire conductivity, but also to identify and quantify sizable and non-linear contact resistances at the buried nanowire–electrode interfaces. Complementing these data with thermal measurements, we obtain a device model further permitting separate extraction of the local thermal nanowire and interface conductivities.

Performance of ring oscillators composed of gate-all-around FETs with varying numbers of nanowire channels using TCAD simulation

In this paper, we investigate the performance of ring oscillators composed of gate-all-around (GAA) silicon nanowire (NW) field-effect transistors (FETs) with four different numbers of NW channels, for sub-10-nm logic applications. Our simulations reveal that ring oscillators with double, triple, and quadruple NW channels exhibit improvements of up to 50%, 85%, and 97%, respectively, in the oscillation frequencies (fosc), compared to a ring oscillator with a single NW channel, due to the large drive current, in spite of the increased intrinsic capacitance of a given device. Moreover, our work shows that the fosc improvement ratio of the ring oscillators becomes saturated with triple NW channels with additional load capacitances of 0.1 fF and 0.01 fF, which are similar to, or less than the intrinsic device capacitance (∼0.1 fF). Thus, our study provides an insight for determining the capacitive load and optimal number of NW channels, for device development and circuit design of GAA NW FETs.

Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes

Stochastic spiking neural networks based on nanoelectronic spin devices can be a possible pathway to achieving "brainlike" compact and energy-effcient cognitive intelligence. The computational model attempt to exploit the intrinsic device stochasticity of nanoelectronic synaptic or neural components to perform learning or inference. However, there has been limited analysis on the scaling effect of stochastic spin devices and its impact on the operation of such stochastic networks at the system level. This work attempts to explore the design space and analyze the performance of nanomagnet-based stochastic neuromorphic computing architectures for magnets with different barrier heights. We illustrate how the underlying network architecture must be modified to account for the random telegraphic switching behavior displayed by magnets with low barrier heights as they are scaled into the superparamagnetic regime. We perform a device-to-system-level analysis on a deep neural-network architecture for a digit-recognition problem on the MNIST data set.

Capacitively Loaded Inverted CPWs for Distributed TRL-Based De-Embedding at (Sub) mm-Waves

In this paper, we present a thru-reflect-line (TRL) calibration/de-embedding kit integrated in the back-end-of-line of a SiGe technology, which allows direct calibration at the first metallization layer, thus moving the reference planes as close as possible to the intrinsic device. The proposed calibration/ de-embedding kit features capacitively loaded inverted CPW lines, allowing to reduce the losses arising from the conducting (i.e., silicon) substrate, by confining the propagating field in the low-loss dielectric layers. The structures have been designed specifically for (sub) mm-wave measurements, as complementary to conventional de-embedding kits used at lower frequencies. A simplified analytical model is presented to support the design of the capacitively loaded CPW lines. Results of a calibration/de-embedding kit, realized using a 130-nm BiCMOS technology are experimentally obtained in the WR-03 waveguide band. Worst case error bounds providing error below 5% in the entire WR3 band are demonstrated. Comparison between direct calibration and de-embedding using calibration transfer from fused silica are provided to highlight the improvements of the proposed approach in the mm-wave bands. Finally, the TRL calibration kit is employed for S-parameter measurements of a heterojunction bipolar transistor and the results are compared to the HiCUM model of the same transistor for verification.

Impact of Embedment of Cu/TaOx/Ru on Its Device Performance

In our previous work, electric performance of Cu/TaOx/Ru has been found to be inferior to that of Cu/TaOx/Pt device. The poor switching properties of the Ru device have been attributed to the degraded inertness properties of the Ru electrode as a stopping barrier for Cu as compared to the Pt electrode. To study this degradation effect further, we have manufactured two nominally identical Cu/TaOx/Ru devices however differently embedded on the Si wafer. While device A is characterized by the layer sequence SiO2-730nm/Ti-20nm/Ru-50nm/TaOx-25nm/Cu-150nm device B has an additional TaOx-30nm layer inserted between SiO2 and Ti layers. We find the electric behavior of the two devices markedly different. Thus the embedment of the device has a major impact on the intrinsic device performance. We explain the difference to be due to high local temperatures >600oC in the device during the switching that cause species interlayer diffusion and trigger undesired chemical reactions.

Impact of Embedment of Cu/TaOx/Ru on Its Device Performance

In our previous work (ECS Trans.75 (32), 13-23, 2017), we have compared the electric performance of Cu/TaOx/Ru and Cu/TaOx/Pt devices finding that the performance of the Ru device is far inferior to that of the Pt device. The poor resistive switching (RS) properties of the Ru device were imputed to the greatly degraded inertness properties of the Ru electrode as a stopping barrier for Cu drift-diffusion. The degraded inertness of the Ru electrode, in turn, has been attributed to larger Cu surface and/or Cu bulk diffusion in Ru than in Pt. The result is surprising as both Pt and Ru are known to be excellent diffusion barriers for Cu in CMOS backend applications. Here, we have manufactured two nominally identical Cu/TaOx/Ru devices, though, differently embedded on the Si wafer. While Ru device A has been manufactured on oxidized Si wafers with 730 nm SiO2 followed by 20 nm of Ti, 55 nm of Ru, 25 nm of TaOx, and 150 nm of Cu, Ru device B has been manufactured in the same way except that a 30 nm TaOx layer has been inserted between SiO2 and Ti layers. Electrical analysis shows that the RS behavior of the two devices is markedly different. Thus the way, nominally identical RS devices are embedded into a technology module has a major impact on the intrinsic device performance. We have identified three major reasons for this disparity. First, the layers of Ti and Ru involved are very thin (20nm and 55 nm). Second, during resistive switching local temperatures at the filament during the form/set and reset operations can exceed 600oC i.e. far higher than the maximum temperature which CMOS backend may experience when the underlying processor is in operation. This temperature is estimated to be ~120oC. Indeed, up to 120oC and above, amorphous Ru remains an excellent diffusion barrier for Cu. The third reason is the crystallinity phase of Ru thin layers that depends on the deposition method and the subsequent ‘unintended’, i.e. related to the RS, local anneals. We find that Ru device A can be switched a limited number of times at high compliance currents Icc (~0.5mA) while the device B at such Icc levels shows either volatile filament formation or when a filament forms, it is permanent. Conversely, at Icc of ~5uA Ru device B shows fairly good RS behavior, while Ru device A shows mostly volatile behavior. Besides Icc, the other critical parameter is the ramp rate rr during the voltage sweep. Both parameters determine effectively the thermal budget during the set and reset operations and are thus responsible for: 1) chemical reactions taking place between the thin metal and dielectric layers and formation of chemical compounds. 2) Cu surface diffusion on the Ru electrode and Cu penetration through the Ru electrode which appears to include compound formation of Ru2Si3 and Cu3Si in case of Ru device A. Therefore, the declared purpose of inserting the TaOx layer between SiO2 and Ti was to prevent those silicidation reactions. In this work, we show that reports in the literature on a number of Ru metallization issues such as: a) thin Ru amorphous films crystallize into a polycrystalline phase at ~550oC; b) observation of a strong diffusive penetration of Cu through the increased number of grain boundaries within Ru layer at 475oC; c) Ru transforms into a less dense Ru2Si3 at ~500oC; d) Ru2Si3 triggers Cu3Si formation at low temperature (~200oC) and degrades the barrier functionality of Ru electrode, are indeed correlated with the differences between the device I-V characteristics of the two Ru devices. Because of the chemical reactions triggered by high local temperatures during cell switching, the Ru devices show new properties over the stable Pt devices. In contrast to Pt devices, the voltage ramp rate has a major impact on the resistance of the on-state, Ron, in the Ru devices: lower ramp rate leads to a higher Ron values because the forming filament is exposed for a longer time to elevated temperatures and suffers from Cu out-diffusion. The observation that Ron in Ru device A is significantly higher than in the Ru device B at the same Icc and rr values, demonstrates that Ru electrode in Ru device B has better inertness properties than in the Ru device A. In summary, this work shows that nominally same device with excellent characteristics in a specific experimental environment, may show vastly degraded characteristics when embedded into a module such as CMOS metallization backend – an issue that has largely been disregarded so far.

Impact of fast transient charging and ambient on mobility of WS2 field-effect transistor

The authors present the impact of fast charging and the ambient on the intrinsic mobility of a WS2 field-effect transistor (FET) by fast pulsed current–voltage (I–V) measurement. Conventional electrical analysis using the direct current (DC) I–V method in air causes charge trapping during measurement, making it impossible to determine the intrinsic device characteristics. Thus, the authors employed the fast pulsed I–V method in vacuum to minimize fast transient charging and interfacial redox-induced charging during measurement. The authors obtained field-effect mobility values of 16.27 and 14.92 cm2/V s in vacuum and air, respectively, using the fast I–V technique; these mobility values were 52%–65% higher than those obtained by the DC method in vacuum and air, respectively. The authors also determined the intrinsic mobility of the WS2 FET using the threshold voltage shift with pulse amplitude.

Verifying Rollett’s Proviso on Active Devices Under Arbitrary Passive Embeddings

Some results implicit in Ohtomo’s original paper are reappraised and built upon to help high-frequency circuit designers avoid common misconceptions. An analysis of the small-signal stability of an intrinsic device is presented, based on a closed-form evaluation of the network determinant in admittance representation and on the relevant Nyquist plot. Since the intrinsic is studied as a three-port, the proposed method represents a rigorous tool for checking the fulfillment of the inherent-stability proviso under arbitrary passive embeddings. Conversely, the proviso is often simply assumed to hold, which can in principle lead to mistakenly predicted circuit stability, or even unconditional stability. Examples of the proposed graphical analysis are provided both for the intrinsic circuit of an actual device and for a modified version thereof, i.e., suitably tweaked for illustrative purposes. The latter example is then expanded to give the reader a full picture of the small-signal stability analysis process, both in a flawed and a correct form.

The Importance of Ballistic Resistance in the Modeling of Nanoscale InGaAs MOSFETs

Physics-based transistor models are important for technology projections and circuit simulations. To date, there has been little discussion on the incorporation of ballistic effects in transistor models. Recent experimental studies have revealed the significance of ballistic transport in the electrical characteristics of nanometer-scale InGaAs MOSFETs with ultra-low external resistance. Without proper accounting for the ballistic resistance and its gate voltage dependence, the access resistance to the intrinsic device cannot be accurately determined, and any physics-based transistor modeling is bound to fail. In this letter, we show that the MIT Virtual Source model, which natively captures ballistic transport physics, correctly incorporates the impact of ballistic resistance. As a result, it accurately models the electrical characteristics of self-aligned nanoscale InGaAs MOSFETs, an excellent model system for near-ballistic transistors, over a broad operational range. We also show that the success of the model development effort crucially relies on the correct extraction of the external source and drain resistance, ${R}_{{\text {sd}}}$ , from experimental measurements.

Recovery of the intrinsic thermoelectric properties of CaMn0.98Nb0.02O3 in 2-terminal geometry using Ag infiltration

Oxide based thermoelectric (TE) materials offer several advantages over currently used intermetallic alloys due to their chemical and thermal stability at high temperatures, non-toxic elements, low cost and ease of manufacture. However, incorporation of oxides into thermoelectric generators (TEGs) is hindered by factors such as the requirement for polycrystalline materials over single crystals and the large electrode/ceramic contact resistances. The latter significantly limits the performance efficiency of a working TEG. Here we report the TE properties of Ag infiltrated polycrystalline CaMn0.98Nb0.02O3 ceramics. We demonstrate that by using this route the intrinsic TE properties of this material are fully recovered in 2-terminal geometry through Ag infiltration, thereby overcoming the electrode TEG contact problem. This synthetic route provides opportunities for bridging the performance gap between the intrinsic TE and TEG device properties of oxides.

Performance Evaluation of Bilayer Graphene Nanoribbon Tunnel FETs for Digital and Analog Applications

The recent advancement in the fabrication of narrow graphene nanoribbon with smooth edges has catalyzed the growth of nanoribbon based transistors. Motivated by these advances, we suggest bilayer graphene nanoribbon tunnel field-effect transistors (BLGNR-TFETs) for low voltage digital and analog applications. The device performance is analyzed by quantum transport simulation, based on self-consistent solutions of two-dimensional Poisson's equation and nonequilibrium Green's function formalism. The results indicate that the use of BLGNR-TFET instead of monolayer graphene nanoribbon TFET with very narrow width, increases the ON current and reduces the intrinsic device delay without lowering the ON/OFF current ratio. The BLGNR-TFET for analog/RF applications has provided higher intrinsic gain at very narrow ribbon width; however, very narrow width reduces the cutoff frequency. Furthermore, RF figure of merits are investigated in the presence of external parasitics.

Tolerance of intrinsic device variation in fuzzy restricted Boltzmann machine network based on memristive nano-synapses

Inspired by the architecture and principle of the human brain, neuromorphic computing has attracted enormous research interest due to its potential for massively parallel and energy-efficient computing, where nanoscale memristors are considered as perfect building blocks for hardware neural networks, serving as compact, analog synapses. However, the inherent variation in memristors has been regarded as a major obstacle to their practical application in neuromorphic computing. Here, for the first time, we demonstrate that this long-standing issue can be addressed by introducing fuzziness into the neural networks. We found that the cycle-to-cycle and device-to-device conductance variations in the on and off states of Pt/TaOx/Ta memristors statistically follow Gaussian distributions, and using an experimentally verified compact synapse model based on the electrical characteristics of Pt/TaOx/Ta devices, a fuzzy restricted Boltzmann machine (FRBM) network was constructed where all the weight states were fuzzified to accommodate device stochasticity. The FRBM network has shown significantly improved tolerance to device variation, as confirmed by increased accuracy in the benchmark test of MNIST handwritten digit classifications. This study thus provides a new route towards highly robust neuromorphic computing, even if the computing elements can be stochastic and inhomogeneous.

Development and validation of ANN approach for extraction of MESFET/HEMT noise model parameters

Most of the transistor noise models refer to the intrinsic device, providing relationships between the transistor noise model parameters and the noise parameters of the intrinsic device. Having in mind that the measured noise parameters correspond to the whole device including the device parasitics, the parameters of the noise models are most often determined by using optimizations in circuit simulators. In this paper, an efficient neural approach for straightforward determination of the noise model parameters, avoiding optimizations, is proposed. A detailed validation of the proposed approach was done by comparison of the measured transistor noise parameters with those obtained by using the extracted noise model parameters for two noise models—the Pospieszalski’s noise model and the noise wave model.

Charge-Based Compact Model for DC Current in Organic TFT Including Non-Linear Injection Effects with a Close Link to Electrical Device Parameter

In this paper a closed-form current model for organic TFTs is presented which leads to a charge-based continuous current model with threshold voltage and slope as model parameters, while still keeping a single expression valid from below to above threshold operation. Most compact models for organic field-effect transistors (OFETs) are based on a two-piece description: a set of equations for above threshold operation is combined with a current model valid in subthreshold region by means of an analytical smoothing function [1]. Thereby the threshold voltage is introduced as fitting parameter without any relation to physical parameters. In [2] a charge-based current model with a continuous equation valid in all regions of operation has been presented. While solving Poisson’s equation the model preserves a close link to physical parameters like shallow and deep trap densities and avoids the introduction of a threshold voltage and subthreshold slope as model parameters. However, from a circuit designer’s perspective a model providing a close link to electrical device parameters is desirable because parameters as threshold voltage and slope can easily be extracted from I/V curves and are performance measures of a device. In this paper an improvement of the model from [2] is presented which leads to a charge-based C∞-continuous current model with threshold voltage and slope as model parameters, while still keeping a single expression valid from below to above threshold operation. To include the effect of hopping transport the empirical power-law mobility model [3] and a contact resistance [4] have been incorporated in the effective mobility. Channel length modulation effects have been included according to [5]. Furthermore, from physical parameters given by trap densities the threshold voltage and subthreshold slope of the device can be calculated. In the case of co-planar device structures the output characteristics in the linear operation regime show a superlinear behaviour due to non-linear injection effects. If the barrier height between source electrode and the channel material is not negligible the channel current is limited by the source injection current. The Schottky barrier height is modulated by the gate and drain potential. A strong electric field causes thinning of the barrier, allowing more carriers to enter channel. An analytical equation for the electric field at the injection barrier has been derived by applying the conformal mapping technique. The bias-dependent lowering of the Schottky barrier, and hence the maximum injection current can be calculated. An equivalent resistance of the Schottky barrier is calculated from the voltage drop Vds and the maximum possible injection current. To arrive at a closed-form current equation for the intrinsic device together with the injecting Schottky barrier this equivalent resistance is incorporated in the current equation by a first order approximation which is commonly used for the consideration of parasitic resistances. In this case the equivalent resistance is bias dependent and reduced with increasing Vds due to Schottky barrier lowering. The model has been validated vs. measurements on devices with small molecule organic semiconductors (Fig. 1, 2). The results show good agreement, even for the 1st and 2nd derivatives of the transfer characteristics. Acknowledgements: This project was funded by the German Federal Ministry of Education and Research contract No.03FH013PX2 (FhProfUnt). This project was also funded by the Horizon 2020 Programme of the European Union under contract RISE 2014 645760 ("DOMINO"). We acknowledge CEA-Liten (Grenoble) and Max Planck Institute for Solid State Research (Stuttgart) for providing measurement data. We thank AdMOS GmbH for support and Keysight Technologies for license donation of IC-CAP.

On the correct interpretation of the low voltage regime in intrinsic single-carrier devices

We discuss the approach of determining the charge-carrier density of a single-carrier device by combining Ohm’s law and the Mott–Gurney law. We show that this approach is seldom valid, due to the fact that whenever Ohm’s law is applicable the Mott–Gurney law is usually not, and vice versa. We do this using a numerical drift-diffusion solver to calculate the current density–voltage curves and the charge-carrier density, with increasing doping concentration. As this doping concentration is increased to very large values, using Ohm’s law becomes a sensible way of measuring the product of mobility and doping density in the sample. However, in the high-doping limit, the current is no longer governed by space-charge and it will no longer be possible to determine the charge-carrier mobility using the Mott–Gurney law. This leaves the value for the mobility as an unknown in the mobility-doping density product in Ohm’s law. We also show that, when the charge-carrier mobility for an intrinsic semiconductor is known in advance, the carrier density is underestimated up to many orders of magnitude if Ohm’s law is used. We finally seek to establish a window of conditions where the two methods can be combined to yield reasonable results.

Device-Circuit Interactions and Impact on TFT Circuit-System Design

This paper reviews the importance of device-circuit interactions (DCI) and its consideration when designing thin film transistor circuits and systems. We examine temperature- and process-induced variations and propose a way to evaluate the maximum achievable intrinsic performance of the TFT. This is aimed at determining when DCI becomes crucial for a specific application. Compensation methods are then reviewed to show examples of how DCI is considered in the design of AMOLED displays. Other designs such as analog front-end and image sensors are also discussed, where alternate circuits should be designed to overcome the limitations of the intrinsic device properties.

Synergy of ammonium chloride and moisture on perovskite crystallization for efficient printable mesoscopic solar cells

Organometal lead halide perovskites have been widely used as the light harvester for high-performance solar cells. However, typical perovskites of methylammonium lead halides (CH3NH3PbX3, X=Cl, Br, I) are usually sensitive to moisture in ambient air, and thus require an inert atmosphere to process. Here we demonstrate a moisture-induced transformation of perovskite crystals in a triple-layer scaffold of TiO2/ZrO2/Carbon to fabricate printable mesoscopic solar cells. An additive of ammonium chloride (NH4Cl) is employed to assist the crystallization of perovskite, wherein the formation and transition of intermediate CH3NH3X·NH4PbX3(H2O)2 (X=I or Cl) enables high-quality perovskite CH3NH3PbI3 crystals with preferential growth orientation. Correspondingly, the intrinsic perovskite devices based on CH3NH3PbI3 achieve an efficiency of 15.6% and a lifetime of over 130 days in ambient condition with 30% relative humidity. This ambient-processed printable perovskite solar cell provides a promising prospect for mass production, and will promote the development of perovskite-based photovoltaics.