Capacitively Loaded Inverted CPWs for Distributed TRL-Based De-Embedding at (Sub) mm-Waves

Abstract

In this paper, we present a thru-reflect-line (TRL) calibration/de-embedding kit integrated in the back-end-of-line of a SiGe technology, which allows direct calibration at the first metallization layer, thus moving the reference planes as close as possible to the intrinsic device. The proposed calibration/ de-embedding kit features capacitively loaded inverted CPW lines, allowing to reduce the losses arising from the conducting (i.e., silicon) substrate, by confining the propagating field in the low-loss dielectric layers. The structures have been designed specifically for (sub) mm-wave measurements, as complementary to conventional de-embedding kits used at lower frequencies. A simplified analytical model is presented to support the design of the capacitively loaded CPW lines. Results of a calibration/de-embedding kit, realized using a 130-nm BiCMOS technology are experimentally obtained in the WR-03 waveguide band. Worst case error bounds providing error below 5% in the entire WR3 band are demonstrated. Comparison between direct calibration and de-embedding using calibration transfer from fused silica are provided to highlight the improvements of the proposed approach in the mm-wave bands. Finally, the TRL calibration kit is employed for S-parameter measurements of a heterojunction bipolar transistor and the results are compared to the HiCUM model of the same transistor for verification.