Intrinsic Dc Gain Research Articles

Impact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective

In this work, influence of interfacial layer thickness on gate-stack based double gate (DG) TFET device concerning analog/RF performance has been studied. Through simulation, it has been found that thicker interfacial layer can be used to mitigate the deprivation inRF/analog performance instigated with high -K gate dielectric. In this article, we have varied the thickness (Ti) of interfacial layer ranging from 0.2 nm to0.7nm and analyzed its effect. The decline in the intrinsic dc gain (δAV = Av(K = 3.9) - Av (K = 40)), maximum oscillation frequency (δfMAX = fMAX(K = 3.9) - fmax(K = 40)) and the cut -off frequency (AfT = fT(K = 39) - fT(K = 40)) is 27.1 dB, 8 GHz and 6.4 GHz, respectively for TI = 0.2nm and24 dB, 1.7 GHz,&3.5 GHz, respectively in case ofTI = 0.7nm which indicates that if interfacial layer is thick (0.7nm), then, it is advantageous as compared to thickness of 0.2nm. Thus, such a device design not only decreases the surface lattice mismatching effect, but also, is more promising for better analog/RF performance of TFET device.

Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the operating temperature from 400 K to 100 K improves the various analog/RF figure of merits (FOMs) of all the three configurations (DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET) of JL-SiNT-FET by considerable expanse. The improvement in intrinsic dc gain (AV) is found to be ~1.8 dB, 2.2 dB, and 1.6 dB respectively for DS-JL-SiNT-FET, D-JL-SiNT-FET, and S-JL-SiNT-FET when the working temperature is reduced from 400 K to 100 K. Additionally, the improvement in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) caused by temperature variation are correspondingly significant in all the three configurations of JLSiNT-FET. It is also observed that the improvement (ΔF = FT=100 - FT=400, where F is the analog/RF FOM) caused by the reduction in temperature is almost similar in all the configurations.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications

In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures of merit (FOM) of the device. With the use of high-K gate dielectric intrinsic dc gain (AV), cut-off frequency (fT), and maximum oscillation frequency (fMAX) degrades. It is observed that the degradation in analog/RF performance when high-K gate dielectrics are used, can be improved by taking higher TI. Furthermore, it is also observed that by using optimal TI (0.7 nm), the variation in ΔAV (AV(K=3.9) - AV(K=40)), ΔfT (fT(K=3.9) – fT(K=40)), and ΔfMAX (fMAX(K=3.9) – fMAX(K=40)) FOMs are almost invariant when outer gate length (Lg) is scaled down from 30 nm to 15 nm. Therefore, it is pertinent to consider higher interfacial layer thickness (~0.7 nm) and lower outer gate length (~ 15 nm) while designing gate-stack based JLSiNT-FET for analog/RF applications.

Analog/RF performance analysis of channel engineered high-K gate-stack based junctionless Trigate-FinFET

In this paper, the effect of channel parameters like channel thickness (TSi) and channel length (Lg) on the analog/RF performance of high-K gate-stack based junctionless Trigate-FinFET (JLT-FinFET) have been studied using TCAD mixed-mode Sentaurus device simulator. It is observed that use of high-K gate dielectric deteriorates the analog/RF performance of the gate-stack based JLT-FinFET. The variation of change in analog/RF FOMs (ΔFOM = FOMK=3.9 - FOMK=40) with respect to channel parameters have been focused throughout this study. It is observed that the deterioration in intrinsic dc gain (ΔAV = (AV(K=3.9) - AV(K=40))) with high-K gate dielectrics aggravates with scaling down of TSi (from 2.31 dB at TSi = 12 nm to 5.2 dB at TSi = 6 nm) but increases marginally with scaling down of Lg (ΔAV = 7.6 dB at Lg = 30 nm and ΔAV = 8.7 dB at Lg = 15 nm). However, the deterioration in maximum oscillation frequency (ΔfMAX) and cut-off frequency (ΔfT) are almost negligible. Moreover, it is also observed that the deterioration in analog/RF FOMs due to high-K gate dielectrics can be reduced by upscaling of interfacial layer thickness (TI). Consequently, higher TI value can be convenient in designing of high-K gate-stack based junctionless Trigate-FinFET at lower TSi for analog/RF applications.

Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET

In this paper, the effect of fringe induced barrier lowering (FIBL) in-conjunction with channel parameters that includes channel thickness (TSi), channel length (Lg) and lateral straggle (σL) on analog and RF performance of FinFET, have been studied using TCAD mixed-mode Sentaurus device simulator. We focused on the variation in analog (intrinsic dc gain) and RF (cut-off frequency) figure of merit (FOM) of high-K gate dielectric based FinFET with respect to channel parameters. It is observed that the variation in intrinsic dc gain (ΔAV) aggravates with TSi scaling. We also observe a mixed response to the ΔAV with respect to variation in Lg and σL, where ΔAV follows an inverse parabolic behavior peaking at an intermediate value of Lg and σL. Variation in cut-off frequency (ΔfT) on the other hand, is negligible (slightly increases with TSi and decreases with Lg and σL). These properties of channel parameters can be handy in designing of high-K gate dielectric based FinFET for analog circuits.

Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET)

In this paper for the first time, the noise immunity and analog performance of nanotube junctionless field effect transistor (NJLFET) has been investigated. Small signal AC performance metrics namely Scattering parameters (S-parameters) have been analyzed along with analog parameters to validate the suitability of NJLFET for RFIC design. NJLFET performance is examined by comparing its performance with junctionless gate-all-around (JLGAA) MOSFET. It has been inferred that NJLFET has improved I on/I off ratio directing improved digital performance at higher channel lengths, reduced channel resistance (R ch) which enables the MOSFET to provide a low resistance path to current and improved early voltage (V EA) which shows the capability for high-gain amplification and higher g m/g d directing high intrinsic dc gain. Higher f Tmax for NJLFET has been observed posing its potential for terahertz applications. Higher gain transconductance frequency product makes NJLFET an ultimate device for high-speed switching applications. Higher maximum transducer power gain in NJLFET implies higher power gain than JLGAA MOSFET. Also, NJLFET exhibits lower harmonic distortion and it has been explained by significant reduction in third-order derivative of transconductance, g m3. Reduction in g m3 shows that NJLFET provides better linearity over JLGAA and is more suitable for RFIC design. Also the S-parameters namely S11, S12, S21 and S22 have been analyzed to verify the small signal performance. A lower magnitude for reflection coefficients S11 and S22 depicts minimum reflection and higher matching between ports in NJLFET than JLGAA MOSFET. Higher voltage gains S12 and S21 are present in NJLFET than its counterpart which shows the higher gains that can be achieved using nanotube architecture. The noise metrics which are noise figure and noise conductance show significant reduction for NJLFET justifying its noise immunity.

Enhancing Low Temperature Analog Performance of Underlap FinFET at Scaled Gate Lengths

Higher mobility and smaller subthreshold slope are some attractive features of low-temperature operation of FinFETs at scaled gate lengths. However, very little effort has been made to enhance the analog performance of the device at lower gate lengths. In this paper, we have studied the low temperature analog performance of underlap FinFET at 16-nm gate length. We have observed that for low-temperature analog operation, high-k gate dielectric is not a viable option at this gate length, as the intrinsic dc gain (A V0 ) decreases with increase in dielectric constant of the gate dielectric because of a pronounced increase in fringe-induced barrier lowering. On the other hand, dual-k spacer-based underlap FinFET is a promising candidate in improving critical analog figures of merit (FOM), such as intrinsic dc gain (A V0 ), cutoff frequency (f T ), and maximum oscillation frequency (f max ) as the temperature is reduced. More so, the percentage increase in FOM of dual-k FinFET is enhanced at lower temperature as well as at lower gate length. Therefore, dual-k spacer underlap FinFET can be a possible solution for further device scaling at low-temperature environment.

Significance of Gate Underlap Architecture in FinFETs for Low-Voltage Analog/RF Applications

In the present work, we analyze the enormous potential of source/drain extension (SDE) region engineering in FinFETs for Ultra Low-Voltage analog/rf applications. We show that SDE region design can simultaneously improve two key analog figures of merit (FOM) - intrinsic dc gain (AVO) and cut-off frequency (fT) for 60 nm FinFETs operated at low drive current (Ids = 5 µA/µm). The results are analyzed in terms of spacer-to- gradient ratio, a new design parameter for devices with non- abrupt source/drain regions. The present work provides new opportunities for realizing future ultra low-voltage/low-power analog/rf design with nanoscale SDE engineered FinFETs.

Comparative analysis of nanoscale MOS device architectures for RF applications

The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T </sub> ) of 25-nm gate-length FinFETs operated at low drain-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> =10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> (~45 dB) and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs

Design and Optimization of FinFETs for Ultra-Low-Voltage Analog Applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic dc gain (A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> ) and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) for 60 and 30 nm FinFETs operated at low drive current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 5 muA/mum). The improved A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VO</sub> and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio-a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

An analytical model is developed for laterally asymmetric channel (graded channel (GC)) design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (>1600 V) and intrinsic DC gain of 70–80 dB for L eff=1.64 μm, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits.