Comparative analysis of nanoscale MOS device architectures for RF applications

Abstract

The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.