Industry Trend: Planar Double Gate Technology

Abstract

Double gate FDSOI device performance improvements over single gate devices have been well documented by many companies in the semiconductor industry, having almost double the drive current, close to ideal subthreshold slope, reduced SCE, and reduced DIBL. However, in the past five years, planar double gate technology has been largely ignored, except for the case of IBM, because of the manufacturing challenges. These include the construction of the bottom gate underneath the FET body, the alignment of the bottom gate to the top gate, and the difficult task of incorporating metal gate or high k dielectric material for the bottom gate formation. From the design and device physics point of view, the planar double gate structure is predicted to behave similarly to single gate with the additional flexibility that the planar double-gate approach allows one to reach the limiting body thickness. In the past year, there has been significant renewed interest based on the increase in reports published by semiconductor companies, research labs and universities on the planar double gate manufacturing process. In this paper, an in-depth analysis will be done to compare industry planar double gate manufacturing methods, including that of Freescale Semiconductor