Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

Abstract

An analytical model is developed for laterally asymmetric channel (graded channel (GC)) design in double gate (DG) silicon-on-insulator (SOI) MOSFETs. Based on modeling, 2D simulation and experimental results, we show DG MOSFETs with laterally asymmetric channel engineering can achieve high values of saturation drain current, exceptionally high values of Early voltage (>1600 V) and intrinsic DC gain of 70–80 dB for L eff=1.64 μm, well in excess of those reported so far. Results of GC DG MOSFETs have also been compared with experimental and simulated data of uniformly doped double and single gate (SG) SOI MOSFETs. The analysis takes into account the effect of length and doping of the high and low doped regions to develop a compact model suitable for device design. The results of analytical model agree well with experimental and simulation data. We propose design guidelines for overall optimum performance of GC DG MOSFETs for realizing future high performance analog circuits.