Inter-stage Inductor Research Articles

Comparison of single event effect on cascoded low noise amplifier performance metrics for two different frequencies

This manuscript examines the impact of single event effects (SEEs) on the well-known cascoded low noise amplifier (LNA) topology connected with an inter-stage inductor sandwiched between the common source (CS) and common gate transistors for boosting the LNA parameters (i.e., gain, etc). In this article, we have considered that the LNA operates at two different frequencies, such as 10 and 30 GHz, in a radiation-prone environment. The effect of SEEs is analyzed in two ways: (i) non-applying a RF input with dc voltage only, and (ii) applying a RF input with dc bias voltage. The first analysis uses basic integration to evaluate the collected charge (QCollected) for a drain terminal momentary current spike with a suitable time period, and the second analysis estimates the LNA output discontinuity (distortion) using a spectrogram (short-time FFT) to determine the radiation strikes on the cascoded LNA. The collected charge is calculated in the temporal analysis, and the discontinuity of LNA’s RF output is analysed using the spectrogram in the frequency domain analysis. From the temporal and frequency analysis, the LNA that operates at a lower frequency (10 GHz) provides more discontinuity in LNA output (causing more disturbance) than the LNA that operates at a higher frequency (30 GHz).

A 21–41-GHz Common-Gate LNA With TLT Matching Networks in 28-nm FDSOI CMOS

A wideband common-gate (CG) cascode low-noise amplifier (LNA) is demonstrated with a 28-nm fully depleted silicon on insulator (FDSOI) CMOS process. Wide bandwidth is achieved with a CG structure in the first stage and tightly coupled ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k=0.86$ </tex-math></inline-formula> ) transmission line transformer (TLT) matching networks. A gm-boosting technique with cross-coupled capacitors improves the gain and noise figure (NF) of the CG amplifier. A high-input 1-dB gain compression point (IP1 dB) can be achieved by introducing an inter-stage inductor at the second-stage cascode amplifier. The LNA shows 19.3 dB gain, 3.1 dB NF, 19.8 GHz (63%) of 3 dB bandwidth, and −15.7 dBm IP1 dB at 28 GHz.

A 26–31 GHz Linearized Wideband CMOS LNA Using Post-Distortion Technique

This paper presents a modified post-distortion (PD) linearization technique for cascode common-gate low noise amplifiers (CG-LNAs) working at high frequencies up to millimeter-wave band. This technique utilizes an auxiliary transistor together with an inter-stage inductor to suppress the third order distortion without degrading gain. The input third order intercept point (IIP3) of the linearized CG-LNA is improved by a factor of up to 12 dB. For demonstration, an mm-wave differential CG-LNA was fabricated based on a 65-nm CMOS process. It achieves 2.4–10.6 dBm IIP3, 9.6–12 dB gain, 5.0–5.45 dB NF over 26–31 GHz and consumes 14.4 mW from a 1.2 V supply.

매칭된 캐스코드 전력 셀 기반 K-/Ka-대역 CMOS 전력 증폭기

This study proposes a K-/Ka-band CMOS power amplifier (PA) with a matched cascode power cell. Interstage inductors are introduced between the common source (CS) and common gate (CG) transistors to achieve high power gain and high reverse isolation of the PA. Cold FETs are configured with interstage inductors to reduce the phase distortion of the PA. The input and output matching networks of the PA are designed as broadside-coupled transformers to obtain a high coupling coefficient and low insertion loss. The proposed PA is fabricated using a 65 nm RF CMOS process, whose chip dimensions are 0.99 mm × 0.57 mm. The device achieves a saturated output power of 19~21 dBm, power-added efficiency of 32~37 %, and power gain of 6.7~7.7 dB in a frequency range of 24~28 GHz. The linear power values for the IMD &lt; −30 dBc are in the range of 12.5~15 dBm in a frequency range of 24~28 GHz.

A solid-state pulse generator based on multilayer ceramic capacitors and insulated gate bipolar transistors.

A solid-state pulse-forming network (PFN) module was designed using multilayer ceramic capacitors (MLCCs). In addition, an all-solid-state pulse generator was fabricated with a Blumlein line that consisted of two PFN single lines and an insulated gate bipolar transistor (IGBT) switch array. This generator was integrated on printed circuit boards (PCBs). The stage capacitors of the PFN were composed of MLCCs connected in series and parallel. To obtain a compact structure, folded, copper-clad wires were used as interstage inductors. The copper-clad wires were structurally optimized to reduce coupling between adjacent interstage inductors. A relatively fast rising waveform edge was obtained using an IGBT gate-boosting circuit and magnetic switch technology. A square-wave pulse with a rise time of 27 ns, a voltage of 5 kV, a width of 120 ns, a maximum repetition rate of 100 Hz, and an evaluated lifetime of 109 pulses was obtained on a load of 6.6 Ω. With its compact size, fast rise time, and long lifetime, the fabricated pulse generator can be used as a component in linear transformer drivers or Marx generators.

A 53–67 GHz Low-Noise Mixer-First Receiver Front-End in 65-nm CMOS

In this paper, we present a mixer-first receiver front-end suitable for millimeter wave (mm-wave) applications. The proposed architecture includes a modified single-balanced mixer core with an on-chip balun in order to provide a differential output from an injected single-ended local oscillator signal. The mm-wave active balun incorporates a cascode cross-coupled structure to achieve a high voltage gain with low amplitude and phase imbalance. The inter-stage inductors are utilized to increase the mixer conversion gain (CG). Moreover, by manipulating the transistor body effect in the transconductance stage, the CG and noise figure of the mixer are further improved. The mixer also achieves a high input return loss which makes it suitable for the mixer-first receivers. As a proof-of-concept, a 53–67 GHz mixer with a center intermediate-frequency of 20 GHz is designed and implemented in a 65-nm CMOS process. The mixer achieves a measured peak conversion gain of 12.1 dB and a 1-dB compression point of −5 dBm. Furthermore, the fabricated mixer achieves a minimum double-sideband (DSB) noise figure of 6.5 dB over its bandwidth. The whole chip consumes 11.5 mW from a 1-V supply and excluding the pads occupies 0.27 mm2 of silicon area.

A 2.3-mW 26.3-GHz $G_{m}$ -Boosted Differential Colpitts VCO With 20% Tuning Range in 65-nm CMOS

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$ ) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively.

A 24–28 GHz high-stability CMOS power amplifier using common-gate-shorting (CGS) technique with 17.5 dBm $${\hbox {P}}_{sat}$$ P sat and 16.3% PAE for 5G millimeter-wave applications

This paper presents a 24–28 GHz high-stability millimeter-wave power amplifier (PA) implemented in low-cost $$0.13\, \upmu \hbox {m}$$ CMOS process. The PA consists of two cascode stages with passive transformer-based input and output baluns. The common-gate-shorting technique is proposed for high-stability and high-gain millimeter-wave cascode stage. To realize this technique, an interdigited powercell structure is adopted for MOS layout optimization. In order to improve $$\hbox {P}_{out}$$ and PAE, an inter-stage inductor is introduced. The proposed PA achieves a PAE over 16.3% with a saturated output power of 17.5 dBm. The maximum gain is 21.2 dB at 26 GHz.

Low-Power CMOS Power Amplifier for 3.1–10.6 GHz Ultra-Wideband Transmitter

ABSTRACTThis paper proposes the design of a low-power ultra-wideband (UWB) power amplifier (PA) in 0.18 µm complementary metal oxide semiconductor (CMOS) technology. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained. The UWB PA employs a forward body biasing technique to reduce power consumption. Meanwhile, in driver stage and power stage of this PA, the resistive feed-back technique with an inter-stage inductor and a series peaking inductors is used to achieve the wider and gain flatness. The post-layout simulation results indicated that the input return loss (S11) was less than −15.8 dB, output return loss (S22) was less than −8.3 dB, and average power gain of 10.6 dB with a flatness about 1.0 dB. The output 1 dB compression point was about 3 dBm. Moreover, a very low power consumption of 14.3 mW was achieved with a die area of 0.96 × 0.95 mm2.

A Technique to Determine the Designable Inductance Value(s) in Wide-Band CMOS-Amplifier System Employing Shunt-Peaking

This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.

A low power and high linearity UWB low noise amplifier (LNA) for 3.1–10.6 GHz wireless applications in 0.13 μm CMOS process

In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1–10.6GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push–pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13μm CMOS process. A gain of 19.5±1.5dB within the entire band was exhibited. The simulated noise figure (NF) was 1–3.9dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56dBm while consuming 4.1mW from a 0.6 power supply was achieved. The simulated input return loss (S11) was less than −5dB from 4.9 to 12.1GHz. The output return loss (S22) was below −10.6dB and S12 was better than −70.6dB.

A High Gain and High Efficiency Cmos Driver Amplifier for 3.5 Ghz WiMAX Applications

A two-stage 0.18μ m CMOS driver amplifier (DA) for WiMAX 3.3 to 3.8 GHz using common source (CS) inductive degeneration is presented in this paper. The first-stage is a modified cascode amplifier with inter-stage inductor matching while the later stage is a conventional CS amplifier. On-wafer measurement shows an average voltage gain of 26.3 dB with 3 dB bandwidth of 0.8 GHz, an output 1 dB compression (P 1 dB) of 12.2 dBm and a power added efficiency (PAE) of 45% at 3.5 GHz while consuming 25 mW from a 1.8 V supply. At 3.5 GHz, the input and output of the proposed amplifier are matched closely to 50 with input and output return losses of –22.9 dB and –24.3 dB respectively. At P 1 dB, it achieved an output third order intercept point (OIP3) of 19.8 dBm. Measurement results obtained in this work could be used as a reference design for immediate drive amplifier implementations in commercial mobile or portable WiMAX transmitter or signal generator.

A 0.18 μm CMOS low noise amplifier using a current reuse technique for 3.1–10.6 GHz UWB receivers

A new, low complexity, ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented. The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure. A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, and a high reverse isolation of −45 dB, and good input/output return losses are better than −10 dB in the frequency range of 3.1−10.6 GHz. An excellent noise figure (NF) of 2.8−4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area, including testing pads, is only 0.8 × 0.9 mm2.

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.

High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique

This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ±135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50 Ω load impedance was achieved with a power consumption of 24-mW.

A 4–17 GHz Darlington Cascode Broadband Medium Power Amplifier in 0.18-$\mu$m CMOS Technology

This letter presents a broadband medium power amplifier in 0.18-μm CMOS technology. The Darlington cascode topology is used to achieve wide bandwidth, flat gain and power frequency response. For wideband matching consideration, an interstage inductor and series peaking RL circuit are adopted. An output high pass matching circuit is used to maintain gain and power flatness at high frequency. The measured results show that the proposed PA demonstrates a gain of 10 dB from 4 to 17 GHz with less than 2-dB ripple, and a saturation output power of 16 to 18 dBm with PAE of better than 10% and power consumption of 306 mW. The chip size is only 0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

DESIGN OF 3 TO 5 GHZ CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM

A single-stage ultra-wideband (UWB) CMOS low noise amplifler (LNA) employing interstage matching inductor on conven- tional cascode inductive source degeneration structure is presented in this paper. The proposed LNA is implemented in 0.18m CMOS technology for a 3 to 5GHz ultra-wideband system. By careful op- timization, an interstage inductor can increase the overall broadband gain while maintaining a low level of noise flgure of an amplifler. The fabricated prototype has a measured power gain of +12.7dB, input return loss of 18dB, output return loss of 3dB, reverse isolation of 35dB, noise flgure of 4.5dB and input IP3 of i1dBm at 4GHz, while consuming 17mW of DC dissipation at a 1.8V supply voltage.