International Technology Roadmap For Semiconductors Research Articles

High-performance monolayer or bilayer SiC short channel transistors with metallic 1T-phase MoS2 contact

In this paper, high-performance monolayer or bilayer SiC short channel transistors with metallic 1T-Phase MoS2 contact have been proposed and investigated by using ab initio simulations. The results show that monolayer or bilayer SiC Schottky-barrier field-effect transistors (SBFET) could conquer the short channel effect, even if the channel length is reduced to 4.1 nm. The p-type ON-currents of monolayer SiC-SBFET, bilayer AB-stacked SiC-SBFET, and bilayer AA-stacked SiC-SBFET are 1132 μA/μm, 980 μA/μm, and 1457 μA/μm, respectively. The all could satisfy the requirement of the high-performance transistor outlined by International Technology Roadmap for Semiconductors (ITRS, 2013 version) for production year 2028. However, the n-type ON-currents of above SiC-SBFETs are 35 μA/μm, 21 μA/μm, and 229 μA/μm, which are much lower than that of p-type ON-currents. Comparing spectral current and spatial local density of states are used to explore the great differences between the p-type and n-type ON-currents.

P-type doping induced performance improvement of two-dimensional SiC transistors with 1T-phase MoS2 electrode

Using nonequilibrium Green's functions in combination with the density-functional theory, we explored the performance of two-dimensional (2D) SiC Schottky-Barrier field effect transistor (SBFET) with different concentration of p-type doping in source/drain region. The corresponding hole Schottky barrier height would be gradually reduced with the increasing of the p-type doping concentration. The ON-state current of SBFETs with different p-type doping concentration (1×1020 cm−2, 5×1020 cm−2, 1×1021 cm−2, 5×1021 cm−2) are 1184 μA/μm, 1263 μA/μm, 1659 μA/μm, 1200 μA/μm, respectively, which could satisfy the ITRS (International technology road-map for semiconductors, 2013 version) high-performance (HP) standards for the 2028 horizon. In addition, the intrinsic gate capacitance, the dynamic power indicator and the intrinsic transistor delay time of p-type doping SBFETs with different doping concentration all satisfy the performance requirement of HP transistor outlined by ITRS.

Guest Editorial: New Perspectives on Roadmapping: Foreword

The papers in this special section focus on the topic of roadmapping. Roadmapping emerged from industrial practice more than five decades ago, initially to support integrated product-technology strategy and planning, and championed by firms, such as Motorola and Philips. The first sector level application of the method was in 1991 by the U.S. National Advisory Committee on Semiconductors, leading to the first international application in 1999 with the publication of the highly influential International Technology Roadmap for Semiconductors (ITRS). Academic interest in the method followed practice, starting in the late 1990s with research groups that had high levels of industrial engagement. Subsequently, there has been a steady growth in both practice and research, with the approach being adopted in a range of sectors, and adapted to address many different strategic goals and organizational contexts. Motivated by continuing developments, this special issue brings together a total of 18 papers covering a diverse range of practice and research perspectives from academia, industry, and government agencies. After a foundational paper setting out definitions, these contributions are organized into five themes: (i) application and practice, (ii) process and methods, (iii) systems design, (iv) policy futures, and (v) digitalization.

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03106 and 3.61106 respectively for 0.179±12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015.

Quantum transport of short-gate MOSFETs based on monolayer MoSi2N4.

The high carrier mobility, appropriate band gap and good environmental stability of two-dimensional (2D) MoSi2N4 enable it to be an appropriate channel material for transistors with excellent performance. Therefore, we predict the performance of double-gate (DG) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on monolayer (ML) MoSi2N4 by ab initio quantum-transport calculations. The results show that the on-state current of the p-type device is remarkable when the gate length is greater than 4 nm, which can meet the high performance requirements of the International Technology Roadmap for Semiconductors (ITRS), 2013 version. Moreover, the gate length can be reduced to 3 nm when an underlap (UL) structure is employed in the MOSFET, and the sub-threshold swing, intrinsic delay time and power consumption also perform well. The calculation results reveal that ML MoSi2N4 will be a promising alternative for transistor channel materials in the post-silicon era.

Accurate Thickness Measurements in Thin Films with Surface Analysis

Quantification in surface analysis using Auger electron spectroscopy and X-ray photoelectron spectroscopy has been the topic of significant work at NPL. A new approach to the quantification of materials that are homogeneous over the analysis volume has been developed using new average matrix relative sensitivity factors. These show agreement between theory and experiment at ~10% for all peaks and elements analysed. For samples that are not homogeneous, layer thicknesses are often required. For ultra-thin gate oxides, the International Technology Roadmap for Semiconductors requires 1.3% accuracy. For this purpose, angle-resolved XPS is a good candidate. In a wide study under the auspices of the Consultative Committee for Amount of Substance (CCQM), the accuracy of measurements of the thicknesses of SiO2 layers <8 nm thick on Si have been assessed. This study involved 45 sets of measurements in laboratories using MEIS, NRA, RBS, EBS, XPS, SIMS, ellipsometry, GIXRR, NR and TEM. The relative strengths and weaknesses become clear. These show that if XPS is used under reference conditions it can be reliable and fast with an accuracy, based on a calibration from the study, ~ 1%. Inter-method correlations as good as 0.05 nm are achieved over the 8 nm range. Furthermore, certain methods, thought to be accurate, suffer from incompleteness of the measurement method. For thicker layers, sputtering is generally used. Here a new method has been tested to generate a sputter yield database, for argon ions, of 26 critical elements. This database has been used to help evaluate a new semi-empirical theory of sputtering yields that includes terms missing from the current semi-empirical theories and removes errors that are up to, and may exceed, a factor of 5. The new theory agrees with published data at ~ 10% and shows why certain elements have anomalously high yields.

TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS

A physical assessment of the lateral gate-all-around (GAA) nanosheet transistor (NSFET) at the G40M16 node (gate length = 12 nm projected for 2028) of the newly defined beyond-Moore International Roadmap for Devices and Systems [~5 nm node of the predecessor International Technology Roadmap for Semiconductors (ITRS)], supported by 3-D numerical device simulations and based on a proposed per-footprint scheme, is presented. The traditional evaluation scheme to gauge the performance of the transistor “per effective channel width” is shown to be improper due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, obfuscates the dependence of current on sheet/channel width and undermines the presumed added benefit of short-channel effect (SCE) control in the GAA device. The NSFET provides a flexible sheet width, as opposed to that of the FinFET with discrete fins, but the allowed range of sheet width is limited due to significant parasitic capacitance at a relatively narrow width and degraded SCE control and increased resistance for desired wide width. Furthermore, the nanosheet (NS) device density is undermined at a narrow width, especially for decreasing pitch. The FinFET is shown to be a favorable alternative to the NSFET even at the G40M16 node.

Quantum transport simulation of the two-dimensional GaSb transistors

Owing to the high carrier mobility, two-dimensional (2D) gallium antimonite (GaSb) is a promising channel material for field-effect transistors (FETs) in the post-silicon era. We investigated the ballistic performance of the 2D GaSb metal–oxide–semiconductor FETs with a 10 nm-gate-length by the ab initio quantum transport simulation. Because of the wider bandgap and better gate-control ability, the performance of the 10-nm monolayer (ML) GaSb FETs is generally superior to the bilayer counterparts, including the three-to-four orders of magnitude larger on-current. Via hydrogenation, the delay-time and power consumption can be further enhanced with magnitude up to 35% and 57%, respectively, thanks to the expanded bandgap. The 10-nm ML GaSb FETs can almost meet the International Technology Roadmap for Semiconductors (ITRS) for high-performance demands in terms of the on-state current, intrinsic delay time, and power-delay product.

Suppression of short channel effects in 5.1 nm WTe2 in-plane Schottky barrier field-effect transistors by Mo-doping

Single layer Schottky barrier field-effect transistors (SBFETs) composed of the in-plane (IP) hetero-junctions of 1T-WTe2(metallic phase WTe2) and 2H–WTe2(semiconducting phase WTe2) have been proposed in this paper. However, the transfer characteristic show that the 5.1 nm IP 1T-2H-1T WTe2 SBFET cannot suppress the short channel effect causing the leakage current beyond the OFF current (IOFF) requirement (0.1 μA/μm) of the International Technology Roadmap for Semiconductors (ITRS, 2013 version) for production in 2028. To solve this problem, we replace the W atoms of 2H–WTe2 near the source electrode with Mo atoms to conquer the short channel effect. We found that the leakage currents of the 5.1 nm IP 1T-2H-1T WTe2 SBFETs decrease gradually with the increase of the number of substitution Mo atoms. When the number of substitutions increases to six periods, the leakage drain current of the 5.1 nm IP 1T-2H-1T WTe2 SBFETs is lower than 0.1 μA/μm. Fortunately, the corresponding ON current (ION) is 961 μA/μm which also conforms to the ON current requirement (900 μA/μm) of ITRS (2013 version) for production in 2028. Therefore, the monolayer WTe2 with the Mo atom substitution also can be used as the channel material in future 5 nm transistor.

High-performance sub-10 nm monolayer black arsenic phosphorus tunneling transistors

Tunneling field-effect transistors (TFETs) based on two-dimensional (2D) materials are expected to break the physical limits of Moore's Law and extend them to the sub-10 nm scope. We systematically study the performance limits of sub-10 nm (6.4–9.6 nm) monolayer (ML) AsP TFETs by means of ab initio quantum transport calculation. With optimized doping, ML AsP TFETs show excellent performance in the armchair transport direction, which is satisfied the requirements of the International Technology Roadmap for Semiconductors (ITRS) and the International Roadmap for Devices and Systems (IRDS 2028 projection) for high-performance (HP) applications in the next ten years in terms of on-state current, delay time, and power consumption per wide power. More encouragingly, ML AsP TFET can still meet the goal of ITRS for low-power (LP) applications even if the gate length is scaled down to 8.7 nm. The on-state current of our proposed AsP TFET is superior to that of TFETs based on InAs, arsenene, antimonene, bismuthene, etc at approximate nodes, making it highly competitive in two-dimensional material semiconductor devices.

Characteristics of Nickel Oxide Modified Zr-Doped HfO2 High-k Thin Films

The high-k thin film can be used to replace SiO2 as the gate dielectric in nano MOS devices to improve the performance and reliability (1,2,3). The HfO2 high-k dielectric suffers from the low crystallization temperature, e.g., <600˚C (4,5). The Zr-doped HfO2 (ZrHfO) dielectric has a higher crystallization temperature and better properties than the undoped HfO2 film based on the same EOT (6-9). The sub 1 nm EOT ZrHfO gate dielectric has been demonstrated (6,10). There are reports that high-k dielectric properties could be improved by dispersing metal particles into the structure (11,12). In this work, the authors investigated changes of material and electrical properties of the ZrHfO gate dielectric by embedding nickel oxide (NiO) into the structure.The ZrHfO/NiO/ZrHfO dielectric stack was sputter deposited on a HF pre-cleaned p-type Si (100) wafer in one-pump down. The bottom and top ZrHfO films were deposited from a Hf/Zr target in Ar/O2 at 5 mTorr for 2 min and 10 min, separately. The NiO film was sputter deposited from a Ni target in Ar/O2 at 5 mTorr for 20s. The PDA was done at 800°C under N2 for 60 sec. The nanocrystalline NiO (nc-NiO) was formed in the dielectric layer, as shown in Figure 1. The gate electrode and backside ohmic contact were formed from the sputter deposited Al. The control sample, i.e., ZrHfO gate dielectric without the embedded NiO, was also prepared for comparison.Figure 2 shows C-V hysteresis curves of the control and nc-NiO embedded samples. All samples show counter-clockwise hysteresis. The control sample has a larger hysteresis than the nc-NO embedded sample has, i.e., 0.2V vs. < 0.02V. The large number of trapped charges in the control sample reflects the incomplete passivation of defects in the PDA step (13,14). The small amount of nc-NiO effectively reduced the oxygen deficiencies or vacancies in the film (13,15). The EOTs of the control and nc-NiO embedded samples are 8 nm and 7.7 nm, respectively. The embedded nc-NiO increase of bulk film’s permittivity due to its dipole moment (16). Similar phenomenon was observed in other nanoparticles embedded high-k stack (11,13).The stress-induced leakage current (SILC) of the capacitor was investigated. The leakage current was measured after stress with a negative gate voltage (-Vg ) for various periods. The leakage current increases with the increase of the stress time, which is attributed to the deterioration of the film (17,18). The nc-NiO embedded sample has a large leakage current than the control sample due to its conductive nature (19).More detailed results on the influence of nc-NiO on the breakdown mechanism using the ramp-relax method will be reported (20).This study was partially sponsored by NSF Grant 0926379. C.-H. Yang thanks Professor Way Kuo of City University of Hong Kong for his advice and support throughout this study. The International Technology Roadmap for Semiconductors. Semiconductor Industry Association, December (2003).C. Hu, Nanotech., 10, 113 (1999).J. J. Lee, X. Wang, W. Bai, N. Lu and D.-L. Kwong, IEEE Trans. Elec. Dev., 50, 2067 (2003).J. Robertson, J. Vac. Sci. Technol. B, 18, 1785 (2000).J. Lu, Y. Kuo, J. Yan and C.-H. Lin, Jpn. J. Appl. Phys., 45, L 901 (2006).Y. Kuo, J. Lu, S. Chatterjee, J. Yan, T. Yuan, H.-C. Kim, W. Luo, J. Peterson and M. Gardner, ECS. Trans., 1, 447 (2006).D. Triyoso, ECS Trans., 3, 463 (2006).Y. Kuo, ECS Trans., 3, 253 (2006).Y. Kuo, ECS Trans., 2, 13 (2006).J. Yan, Y. Kuo, and J. Lu, ECS Solid-State Lett., 10, H199 (2007).R. Ravindran, K. Gangopadhyay, S. Gangopadhyay, N. Mehta, and N. Biswas, Appl. Phys. Lett., 89, 263511 (2006).G. C. Vezzoli, M. F. Chen, and J. Caslavsky, Ceram. Int., 23, 105 (1997).C.-H. Lin and Y. Kuo, J. Electrochem. Soc., 158, G162 (2011).N. Zhan, M. C. Poon, C. W. Kok, K. L. Ng, and H. Wong, J. Electrochem. Soc., 150, F200 (2003).H. Sim, H. Chang, and H. Hwang, Jpn. J. Appl. Phys. Part 1, 42, 1596 (2003).S. C. Chung, S. Krüger, G. Pacchioni, and N. Rösch, J. Chem. Phys., 102, 3695 (1995).S. Chatterjee, Y. Kuo, J. Lu, J.-Y. Tewg, and P. Majhi, Microelec. Rel., 46, 69 (2006).S. Chatterjee, Y. Kuo, J. Lu, Microelec. Eng., 85, 202 (2008).J. Feinleib and D. Adler, Phys. Rev. Lett., 21(14), 1010 (1968).W. Luo, Y. Kuo and W. Kuo, IEEE Trans. Dev. Mat. Rel., 4, 488 (2004). Figure 1

The in-plane graphene and boropheneβ12 contacted sub-10 nm monolayer black phosphorous Schottky barrier field-effect transistors

Using ab initio quantum transport calculations, we investigate the performance of the in-plane (IP) graphene and boropheneβ12 contacted sub-10 nm (gate length = 5.1, 6.1, 7.3, 8.8 nm) single-gated (SG) and double-gated (DG) monolayer (ML) black phosphorous (BP) Schottky barrier field-effect transistors (SBFETs). The transfer characteristics, total gate capacitance, intrinsic delay time and dynamic power indicator are studied. The calculated on-state currents of the IP graphene contacted sub-10 nm SG ML BP SBFETs are 1064.8, 1272.3, 1676.5, 1363.8 μA/μm, which are far beyond the requirements of International Technology Roadmap for Semiconductor (ITRS) high performance (HP) application targets. Compared with graphene electrode, the on-state currents of IP boropheneβ12 contacted sub-10 nm SG ML BP SBFETs can only satisfy about 10%–70% requirement of HP standards because of the strong metal induced gap states (MIGS) in the channel. Moreover, we further investigated the effect of DG model on the device performance. The results indicated that the gate electrostatic control is significantly improved by using DG model. The on-state currents of IP graphene and boropheneβ12 contacted sub-10 nm DG ML BP SBFETs are increased by a factor of 1.37–1.56 and 1.16–3.59 compared with SG model. As a result, the large on-state currents of IP configurations based on graphene/ML BP/graphene can greatly stimulate the potential of BP transistors.

Promising Properties of a Sub-5-nm Monolayer MoSi2N4 Transistor

Two-dimensional (2D) semiconductors have attracted tremendous interests as natural passivation and atomically thin channels that could facilitate continued transistor scaling. However, air-stable 2D semiconductors with high performance were quite elusive. Recently, extremely air-stable MoSi2N4 monolayer had been successfully fabricated [Hong et al., Science 369, 670 (2020)]. To further reveal its potential applications in the sub-5 nm MOSFETs, there is an urgent need to develop integrated circuits. Here we report first-principles quantum transport simulations on the performance limits of n- and p-type sub-5 nm monolayer (ML) MoSi2N4 metal-oxide-semiconductor FETs (MOSFETs). We find that the on-state current in the MoSi2N4 MOSFETs can be effectively manipulated by the length of gate and underlap (UL), as well as the doping concentration. Very strikingly, we also find that the n-type devices the optimized on-state current can reach up to 1390 and 1025 uA/um for the high performance (HP) and low power (LP) applications, respectively, both of which satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements. Whereas, the optimized on-state current can meet the LP application (348 uA/um) for the p-type devices. Finally, we find that the MoSi2N4 MOSFETs have ultra-low subthreshold swing and power delay product, which have potential to realize the high speed and low power consumption devices. Our results show that MoSi2N4 is an ideal 2D channel material for future competitive ultrascaled devices.

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length.

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

Reliability and Power Analysis of FinFET Based SRAM

Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices and architecture such as FinFET devices instead of MOSFET. FinFET emerged as a non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering and threshold voltage roll-off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work the reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductors) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7 nm BSIM-CMG Predictive technology model files (PTM) in mentor graphics tool. The FinFET based SRAM showed low leakage, low power dissipation, and less delay compared to existing conventional MOSFET based SRAM.

Impact of the Bitcell Topology on the Multiple-Cell Upsets Observed in VLSI Nanoscale SRAMs

This article presents an analysis of the multiple events [and more specifically, multiple-cell upsets (MCUs)] that may occur at successive generations of bulk CMOS static random access memories (SRAMs) operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS)/International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90- and 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various commercial-off-the-shelf (COTS) SRAMs manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45 down to 14 nm).

Design of a Capacitorless Dynamic Random Access Memory Based on Ultra-Thin Polycrystalline Silicon Junctionless Field-Effect Transistor with Dual-Gate.

In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with an ultrathin polycrystalline silicon layer was designed and investigated by using technology computer-aided design simulation (TCAD). The application of a negative voltage at the control gate results in the generation of holes in the storage region by the band-to-band tunneling (BTBT) effect. Memory characteristics such as sensing margin and retention time are affected by the doping concentration of the storage region, bias condition of the program, and length of the intrinsic region. In addition, the gate acts as a switch that controls the transfer characteristics while the control gate plays a role in retaining holes in the hold state. The device was optimized, considering various parameters such as the doping concentration of the storage region (Nstorage), intrinsic region length (Lint), and operation bias conditions to obtain a high sensing margin of 49.7 μA/μm and a long retention time of 2 s even at a high temperature of 358 K. The obtained retention time is almost 30 times longer than that predicted for modern DRAM cells by the International technology roadmap for semiconductors (ITRS).

Lateral heterostructures of zigzag phosphorene nanoribbons as a platform for high performance 5 nm transistor

By performing first-principle transport calculations, we propose that lateral heterostructures of zigzag phosphorene nanoribbons (ZPNRs) with the different passivated edges, can represent a powerful platform for the high performance field-effect transistors (FETs). The ZPNR with H-passivated edge is a semiconductor with a band gap of 1.39 eV. However, the ZPNRs with zigzag edges and cliff edges all exhibit the metallic characters. Two 5 nm Schottky barrier FETs consisting of H-passivated ZPNR and unpassivated ZPNRs with zigzag or cliff edges all can overcome the short channel effect. More importantly, the 5 nm Schottky barrier FET consisting of H-passivated ZPNR and unpassivated ZPNRs with cliff edge at a supply voltage of 0.64 V exhibits ION/IOFF ratio larger than 103, which satisfy the requirements of the high-performance transistor outlined by the ITRS (International Technology Roadmap for Semiconductors). Therefore, the transistor model of ZPNRs in this paper provides a valuable idea for the design of short channel transistors in the future.

Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

AbstractUtilizing the layer‐controlled bandgap of a 2D material is an effective way of improving a tunneling field‐effect transistor (TFET) device's performance because of the narrowing tunneling barrier. An ab initio quantum transport method is used to study the SnS homojunction TFETs at a sub‐10 nm scale through layer controlling. The optimal SnS homojunction TFET has a bilayer SnS as the source electrode, which possesses a low leakage current like the ML SnS TFET and a high on‐state current like the BL SnS TFET. The low SSave_4dec (subthreshold swing over four decades of the drain currents) of ≈47–48 mV dec−1 and I60 (drain current at 60 mV dec−1) of ≈1.1–1.2 µA µm−1 implies the BL source SnS TFET, a fast low‐power (LP) device. The optimal BL source SnS TFET with a gate length of Lg = 10 nm exceeds the LP device requirement of the International Technology Roadmap for Semiconductors (ITRS) (2013 version), and its negative capacitance counterparts can exceed the ITRS 2028 target for LP device at Lg = 5 nm.

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ) and high power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce a new transformer-based series output combiner design method to achieve a true-Doherty load modulation that uses a compact footprint. The output stages of the main PA and the auxiliary PA (aux. PA) both use a differential three-stacked FET topology for high output power without posing a reliability issue. The intermediate-node matching is achieved by using a shunt inductor for voltage waveform alignment and efficiency improvement. A modified differential quadrature hybrid is proposed to achieve the desired quadrature power splitting function without the need for an input balun. For the proof of concept, the proposed PA is implemented in a 22-nm CMOS fully depleted silicon-on-insulator (FD-SOI) technology with a core area of 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . At 28 GHz, the measured saturated output power ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ), 1-dB output compression point (OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ), and peak power-added efficiency (PAE) are 22.5 dBm, 21.1 dBm, and 28.5%, respectively. State-of-the-art International Technology Roadmap for Semiconductors (ITRS) figure-of-merit (FOM) and power density are achieved. The measured PAE at 6-dB PBO is 22.1%, which results in an efficiency enhancement ratio of 1.56/3.12 with respect to an ideal class-B and class-A PA. The proposed PA can support 2.4-Gb/s 64-quadratic amplitude modulation (64-QAM) and 0.8-Gb/s 256-QAM signal with a competitive average PAE. Excellent device reliability is validated by operating the implemented PA under 3-dB gain compression point for 12 h with less than 0.06-dB P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> variation. The proposed Doherty PA with a compact footprint is suitable for the integration purpose of future 5G multiple-input multiple-output (MIMO) and phased-array applications.