Reliability and Power Analysis of FinFET Based SRAM

Alluri Navaneetha,Kalagadda Bikshalu

doi:10.1007/s12633-021-01345-4

Alluri Navaneetha, Kalagadda Bikshalu

Open Access

https://doi.org/10.1007/s12633-021-01345-4

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Journal: Silicon	Publication Date: Sep 10, 2021
Citations: 3	License type: cc-by

Affiliation: Kakatiya University

Abstract

Demand for accommodating more and new functionalities within a single chip such as SOC needs novel devices and architecture such as FinFET devices instead of MOSFET. FinFET emerged as a non-planar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering and threshold voltage roll-off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed. Reliability is one of key considerations in converting a proof of concept into reality. In this work the reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductors) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7 nm BSIM-CMG Predictive technology model files (PTM) in mentor graphics tool. The FinFET based SRAM showed low leakage, low power dissipation, and less delay compared to existing conventional MOSFET based SRAM.

Highlights

Electronic devices are in high demand in the electronics sector and are utilized in a variety of applications including automobiles, computing, communications, entertainment, artificial intelligence, neural networks, computer vision, big data, and many others [1], in which advanced nanodevice FinFET is used as a transistor instead of MOSFET to achieve high performance, low power dissipation, low area at reduced technology
Channel electrostatics is controlled by single gate MOSFET whereas control of channel in 3 directions to reduce short channel effects is achieved by 3 gate FinFET [2, 3] For digital circuit, Mixed signal circuit, Analog/RF circuit, FinFET is emerged as superior device to get low power dissipation, high speed, low area at deep submicron range
Simulation results are carried out for 7nm FinFET based SRAM to analyze the parameters for leakage power, delay and power dissipation which is compared with existing MOSFET device. 7nm FinFET based SRAM shown less leakage, low power, high speed compared to the existing MOSFET based SRAM device as shown in comparison table (Table-1)

Summary

Introduction

Electronic devices are in high demand in the electronics sector and are utilized in a variety of applications including automobiles, computing, communications, entertainment, artificial intelligence, neural networks, computer vision, big data, and many others [1], in which advanced nanodevice FinFET is used as a transistor instead of MOSFET to achieve high performance, low power dissipation, low area at reduced technology. Channel electrostatics is controlled by single gate MOSFET whereas control of channel in 3 directions to reduce short channel effects is achieved by 3 gate FinFET [2, 3] For digital circuit, Mixed signal circuit, Analog/RF circuit, FinFET is emerged as superior device to get low power dissipation, high speed, low area at deep submicron range. Due to the presence of an insulating layer beneath oxide, SOI FinFETs with lower parasitic capacitance increases switching speed and reduces power consumption [4]. Due to several advantages FinFET can be used in variety of application such as terrestrial systems, infrared detectors, space, satellite communication, nuclear reactor, military [12,13]

Reliability Study Of Finfet

Electromigration Assessment of the FinFET device post bonding

Findings

Conclusion