International Technology Roadmap For Semiconductors Research Articles

High-Performance Sub-10 nm Two-Dimensional SbSeBr Transistors through Transport Orientation.

Exploring two-dimensional (2D) materials with a small carrier effective mass and suitable band gap is crucial for the design of metal oxide semiconductor field effect transistors (MOSFETs). Here, the quantum transport properties of stable 2D SbSeBr are simulated on the basis of first-principles calculations. Monolayer SbSeBr proves to be a competitive channel material, offering a suitable band gap of 1.18 eV and a small electron effective mass (me*) of 0.22m0. The 2D SbSeBr field effect transistor (FET) with 8 nm channel length exhibits a high on-state current of 1869 μA/μm, low power consumption of 0.080 fJ/μm, and small delay time of 0.062 ps, which can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices. Moreover, despite the monolayer SbSeBr having an isotropic me*, the asymmetrical band trends enable SbSeBr FETs to display transport orientation, which emphasizes the importance of band trends and provides valuable insights for selecting channel materials.

SiX2 (X = S, Se) Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.

The gate-all-around (GAA) field-effect transistor (FET) holds great potential to support next-generation integrated circuits. Nanowires such as carbon nanotubes (CNTs) are one important category of channel materials in GAA FETs. Based on first-principles investigations, we propose that SiX2 (X = S, Se) nanowires are promising channel materials that can significantly elevate the performance of GAA FETs. The sub-5 nm SiX2 (X = S, Se) nanowire GAA FETs exhibit excellent ballistic transport properties that meet the requirements of the 2013 International Technology Roadmap for Semiconductors (ITRS). Compared to CNTs, they are also advantageous or at least comparable in terms of gate controllability, device dimensions, etc. Importantly, SiSe2 GAA FETs show superb gate controllability due to the ultralow minimum subthreshold swing (SSmin) that breaks "Boltzmann's tyranny". Moreover, the energy-delay product (EDP) of SiX2 GAA FETs is significantly lower than that of the CNT FETs. These features make SiX2 nanowires ideal channel material in the sub-5 nm GAA FET devices.

High-performance Schottky-barrier field-effect transistors based on two-dimensional GaN with Ag or Au contacts

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

Polythiophene-based organic transistors：Time to a single nanowire and sub-5 nm gate length

Future organic field-effect transistors (FETs) may utilize one-dimensional (1D) semiconductor materials in their channels. In this study, we used the ab initio method to explore the transport characteristics of 1D nanowire polythiophene FETs comprehensively. Based on the 2028 map in the International Technology Roadmap for Semiconductors (ITRS) in 2013, our theoretical simulations showed that n-type and p-type gate-all-around (GAA) 1D polythiophene FETs with 5-nm gate length (Lg) and appropriate underlap (UL) satisfy the basic high-performance and low-power-consumption device applications. Moreover, both the n-type and p-type GAA 1D polythiophenee FETs (Lg = 3 nm) meet the high-performance needs of ITRS. Our numerical results revealed that the organic transistors can be designed by using a single nanowire and the minimum Lg of transistors can scale to 3 nm.

Sub-5 nm Ultrathin In2O3 Transistors for High-Performance and Low-Power Electronic Applications.

Ultrathin oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, ultrathin indium oxide (In2O3) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibit an extremely high drain current (104 μA/μm) and transconductance (4000 μS/μm). Here, we employ ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length (Lg) ultrathin In2O3 FETs. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of ultrathin In2O3 FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of ultrathin In2O3 (3.0 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Notably, both the HP and LP ultrathin In2O3 FETs exhibit superior energy-delay products as compared to those of other common 2D semiconductors such as monolayer MoS2 and MoTe2. These findings unveil the potential of ultrathin In2O3 in HP and LP nanoelectronic device applications.

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Performance limits exploration of sub-5 nm monolayer germanane transistors: A first-principle quantum transport simulation

Two-dimensional germanium is considered a promising new channel material to replace silicon owing to its lower effective mass and larger electron–hole mobility. To investigate the transport characteristics of single-layer germanane transistors with gate lengths (Lg) below 5 nm, we utilize an ab initio quantum transport methodology. It was found that the n-type germanane transistors having Lg of 3 and 5 nm satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for the on-state current (Ion), effective delay time, and power-delay products of high-performance (HP) devices. Notably, by introducing a negative capacitive (NC) dielectric layer, the p-type germanane transistor having an Lg of 5 nm is almost able to meet the ITRS demands for HP devices. Despite reducing the gate length to 2 nm through the incorporation of the NC dielectric layer, the on-state currents for both n-type and p-type still satisfy approximately 80% of the ITRS standard. Therefore, monolayer germanane presents promising potential as a channel material in a sub-5 nm scale for HP applications.

Low-Power Transistors with Ideal p-type Ohmic Contacts Based on VS2/WSe2 van der Waals Heterostructures.

Achieving low-resistance Ohmic contacts with a vanishing Schottky barrier is crucial for enhancing the performance of two-dimensional (2D) field-effect transistors (FETs). In this paper, we present a theoretical investigation of VS2/WSe2-vdWHs-FETs with a gate length (Lg) in the range of 1-5 nm, using ab initio quantum transport simulations. The results show that a very low hole Schottky barrier height (-0.01 eV) can be achieved with perfect band offsets and reduced metal-induced gap states (MIGS), indicating the formation of p-type Ohmic contacts. Additionally, these FETs also exhibit an impressive low subthreshold swing (SS) (69 mV/dec) and high Ion/Ioff (>107) with an appropriate underlap (UL) structure consisting of pristine WSe2. Furthermore, even when the Lg is scaled down to 3 nm, the device can still meet the low-power (LP) requirements of the International Technology Roadmap for Semiconductors (ITRS) by controlling the UL. Consequently, this study provides valuable insights for the future development of LP 2D FETs.

Towards ultralow-power and high-speed electronics: Tunnel transistor based on single-chain Tellurium

The application of tunnel field-effect transistors (TFETs) in the sub-5.1 nm range meets the challenges of low on-state current (Ion), elevated leakage current (Ileak) and a limited bias range with sub-thermionic subthreshold swing (SS) characteristics. Here, by the design of gate-all-around (GAA) single-chain Te (1Te) TFETs, the sub-thermionic SS characteristics span nearly six orders of magnitude of drain current, overcoming the above challenges. While there usually exists trade-offs between maximizing Ion and minimizing Ileak, our optimized 5.1 nm GAA 1Te TFET defies this convention. Its steep turn-on characteristics result in an ultra-low Ileak of 7.9 × 10−10 μA/μm coupled with a high Ion of 1352 μA/μm, surpassing other low-dimensional materials-based FETs. These exceptional performances are attributed to the desirable properties from ultra-thin 1Te, including its moderate bandgap, anisotropic effective mass, and reduced screening length. Crucially, this device demonstrates key figure of merits for digital electronics that fulfill both the requirements of high-performance and low-power device specified by the International Technology Roadmap for Semiconductors, indicating the potential as energy-efficient and high-speed electronic switch. Our findings are expected to stimulate further research into sub-5.1 nm quasi-1D materials-based TFETs and provide valuable insights for optimizing their performance.

The interfacial properties of 2D metal-monolayer blue phosphorene heterojunctions and transport properties of their field-effect transistors

Monolayer blue phosphorene (BlueP) has attracted much interest as a potential channel material in electronic devices. Searching for suitable two-dimensional (2D) metal materials to use as electrodes is critical to fabricating high-performance nanoscale channel BlueP-based field effect transistors (FETs). In this paper, we adopted first-principles calculations to explore binding energies, phonon calculations and electronic structures of 2D metal-BlueP heterojunctions, including Ti3C2-, NbTe2-, Ga(110)- and NbS2-BlueP, and thermal stability of Ti3C2-BlueP heterojunction at room temperature. We also used density functional theory coupled with the nonequilibrium Green function method to investigate the transport properties of sub-5 nm BlueP-based FETs with Ti3C2-BlueP electrodes. Our calculated results indicate that Ti3C2-BlueP has excellent thermal stability and may be used as a candidate electrode material for BlueP-based FETs. The double-gate can more effectively improve the device performance compared with the single-gate. The estimated source leakage current of sub-5 nm transistors reaches up to 369 µA µm−1, which is expected to meet the requirements of the international technology roadmap for semiconductors for LP (low-power) devices. Our results imply that 2D Ti3C2 may act as an appropriate electrode material for LP BlueP-based FETs, thus providing guidance for the design of future short-gate-length BlueP-based FETs.

Scaling limits of monolayer AlN and GaN MOSFETs

The shrinking of transistors to ultra-scale limits is in great demand to extend Moore’s law, where the search for proper alternative channel materials is significant. The III-V group compounds are regarded as post-Si candidates for their high electron mobility. Herein, we simulate the monolayer (ML) AlN and GaN metal–oxidesemiconductor field-effect transistors (MOSFETs) with ab initio quantum transport simulation to evaluate their scale limit. The ML AlN and GaN MOSFETs exhibit much better n-type performances than their p-type counterparts, and the n-type ML AlN (GaN) MOSFETs can surpass the International Roadmap for Device and Systems (IRDS, 2022 version) lower-power (LP) and high-performance (HP) target for the year 2028 even at gate length (Lg) of 3 and 2 nm, respectively. Encouragingly, the optimal n-type ML AlN (GaN) MOSFETs possess the highest (second-highest) Ion against all studied n-type ML MOSFETs and propel the Lg limit that outperforms the International Technology Roadmap for Semiconductors (ITRS, 2013 version) LP and HP targets to 2 and 1 (2) nm, respectively.

Ultrahigh current and ultralow power dissipation of Janus monolayer IIIA-VIA Ga2XY MOSFETs

With the advances of two-dimensional semiconductors, it is promising for the miniaturization of highly integrated circuits. However, the high leakage current, small on-state current and unnecessary power consumption hinder the development of high-performance nanodevices. Here, we design sub-5-nm double-gate monolayer Ga2XY (X, Y = S, Se and Te) metal–oxidesemiconductor field-effect transistors. For all the designed devices, the on-state current, intrinsic delay time and power delay product can meet the standard of the International Technology Roadmap for Semiconductor in 2028. Additionally, the devices based on large bandgap materials have strong inhibition effect on leakage current. In particular, the Ga2SSe device has optimized subthreshold swing as low as 60.7 mV/dec and Ion of 5082 μA/μm (about 6 times higher than the high-performance requirements). The extremely low energy-delay product of 3.64 × 10−31 Js/μm is obtained for the Ga2SeTe device. Therefore, monolayer Ga2XY can be expected for the application of next-generation high-performance electronic nanodevices.

Geometric, Electronic, and Transport Predictions on Two-Dimensional Semiconducting Silicon with Kagome Lattice: Implications for Nanoscale Field-Effect Transistor Applications

Two-dimensional (2D) semiconducting silicon (Si) is significant for the development of micro/nanoelectronics because of their compatibility with the current Si-based technology and the advantages common to 2D electronic materials. Here, by focusing on the kagome lattice (KL), we design a set of semiconducting 2D KL-Si for nanoscale field-effect transistor (FET) applications. First-principles calculations demonstrate that both stable geometric properties and tunable semiconducting electronic properties can be obtained for the 2D KL-Si with different thicknesses. The 2D KL-Si features electronic band gaps ranging from 2.82 to 1.36 eV as a function of increasing the layer thickness and hole/electron mobility as large as about 103 cm2·V–1·s–1. By applying the KL-Si to nanoscale FETs, we obtain giant negative differential resistances with peak-valley ratios over 107 and excellent switching performance fulfilling the requirements of the International Technology Roadmap for Semiconductors. Our study demonstrates the importance of kagome topology in the design of 2D Si crystals with excellent semiconducting properties as well as their promising application in nanoelectronic devices.

Sub‐5 nm 2D Semiconductor‐Based Monolayer Field‐Effect Transistor: Status and Prospects

A detailed review of sub‐5 nm 2D semiconductor monolayer (ML) field‐effect transistors (FETs) is presented. A brief introduction to the fundamentals of 2D materials and their properties is provided followed by a critical review to propose an appropriate channel material from the available 2D materials. Various device simulation techniques incorporating density functional theory (DFT) and nonequilibrium Green's function (NEGF) are discussed in order to comprehend the distinctive features of 2D materials and the ballistic performance of sub‐5 nm ML 2D FETs. Relevant, recent experimental progress is also discussed. The review suggests that sub‐5 nm monolayer FETs based on 2D semiconductors like black phosphorene, WSe2N4, silicene, tellurene, arsenene, WSe2, MoTe2, MoS2, InSe, α‐CS, MoSi2N4, WS2, Bi2O2Se, GeSe, SnSe2, SnS2, AsP, GeS, MoSi2N4, BiH, SnSe2 and MoTe2 show excellent device performance meeting the International Technology Roadmap for Semiconductor (ITRS) requirements (2013 Version) for both high‐performance (HP) and low‐power (LP) applications in terms of on‐state current, subthreshold swing (SS), delay time, and power delay product (PDP).

Extreme Anisotropic Dispersion and One-Dimensional Confined Electrons in 2-D SiP₂ FETs With High Transmission Coefficients

2-D semiconductors are promising Si alternatives for channels in next-generation electronic devices. Considering the 2-D SiP2 with unique dispersion at the band edge and intrinsic P–P chains with 1-D confined electrons, we provide a comprehensive investigation on the electronic and ballistic transport properties of SiP2. Based on first-principle and ballistic quantum transport simulations, the 2-D SiP2 exhibits a strong anisotropy in both geometric structures and electronic properties, playing a critical role in the anisotropy of transmission path and device performance for SiP2 field-effect transistors (FETs). Considering the ultrahigh saturation current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {sat}}$ </tex-math></inline-formula> ) of SiP2 FETs in along-chain direction, the transfer characteristic with different gate lengths (3–12 nm) is calculated to thoroughly evaluate the performance. As a result, 5–12 nm SiP2 n-FETs with underlap (UL) configuration can fulfill the International Technology Roadmap for Semiconductors (ITRS) and International Roadmap for Devices and Systems (IRDS) goals, showing an ultrahigh ON-state current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3420 ~{\mu } \text{A}/ {\mu } \text{m}$ </tex-math></inline-formula> with 10 nm gate length. In addition, the figures of merits, such as delay time and power dissipation, are comprehensively assessed, proving the fast-switching and low-energy consumption ability of SiP2 FETs. Hence, our study demonstrates the great potential of 2-D SiP2 for future competitive electronic devices.

Symmetric and Excellent Scaling Behavior in Ultrathin n‐ and p‐Type Gate‐All‐Around InAs Nanowire Transistors

AbstractComplementary metal‐oxide‐semiconductor (CMOS) field‐effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µe than silicon but suffers from a much lower hole mobility µh (µe/µh = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum‐transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub‐2‐nm‐diameter gate‐all‐around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short‐channel effects are effectively depressed in the symmetric n‐ and p‐type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits.

Designing sub-5 nm monolayer AlP MOSFETs

Two dimensional (2D) materials have appealed to great interest for microelectronics in developing the next era of metal-oxide-semiconductor field-effect transistors (MOSFETs). 2D aluminum phosphorous (AlP) with constancy under ambient settings is a suitable channel material for the next MOSFET era. Based on the ab initio quantum transport simulation, we investigate the device performance of the n and p-type sub-5 nm monolayer (ML) AlP MOSFETs. The ML AlP MOSFETs could be satisfied the International Technology Roadmap for Semiconductors (ITRS) standard 2028 by their optimal parameters; on-state current (Ion), delay time (τ), and power dissipation (PDP) for the high-performance (HP)/low-power (LP) devices even after the gate length is lowered to 4/5 nm for n-type and 3/5 for p-type respectively. As a result, AlP is a channel candidate that could be considered for use in the next era of MOSFETs.

Optimization of 14 nm double gate Bi-GFET for lower leakage current

In recent years, breakthroughs in electronics technology have resulted in upgrades in the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy contenders due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene FET with a high-k/metal gate is proposed, which is composed of hafnium dioxide (HfO 2 ) and tungsten silicide (WSi x ) respectively . It is simulated and modelled using silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools, as well as the Taguchi L9 orthogonal array (OA). The threshold voltage (V TH ) adjustment implant dose, V TH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters. While the V TH adjustment tilt angle and the S/D implant tilt angle have both been investigated as noise factors. When compared to the initial findings before optimization, the I OFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an I OFF of 28.564 nA/µm, which is closer to the international technology roadmap semiconductor (ITRS) 2013 target than before.

Prediction of Semiconducting 2D Nanofilms of Janus WSi2P2As2 for Applications in Sub-5 nm Field-Effect Transistors

Searching for eligible two-dimensional (2D) semiconductors to fabricate high-performance (HP) short-channel field-effect transistors (FETs) at the nanoscale is essential toward the continuous miniaturization of devices. Herein, we predict the 2D Janus WSi2P2As2 semiconductor and propose it as a qualified channel material for sub-5 nm FETs by using first-principles calculations. The results demonstrate that the monolayer Janus WSi2P2As2 is a 2D semiconducting nanofilm with a band gap of 0.83 eV, a hole mobility of 490 cm2 V–1 s–1 in the armchair direction, and an out-of-plane polarization. Benefiting from these outstanding intrinsic characteristics, the performance of the 5 and 3 nm gate-length WSi2P2As2 FETs can fulfill the International Technology Roadmap for Semiconductors for HP standards after employing optimizing strategies, including underlap structure, dielectric project, and cold source. Our results promote the development of new 2D nanomaterials and device architectures for designing HP short-channel FETs.

Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling

Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.