Intermetal Dielectric Research Articles

Investigations and detections on a new BEOL dielectric failure mechanism at advanced technologies

The ultra-low k dielectrics have been widely used as semiconductor technology steps into 45nm, 28nm, and more advanced nodes. Combined with the rapid shrinks of critical dimensions, the ultra-low k dielectrics face challenges to retain the benefits of interconnect scaling both on their manufacturability and reliability performances. In this paper, abnormal failure phenomena were investigated on 28nm ILD (Intra Level Dielectric) and IMD (Inter Metal Dielectric) qualifications and 40nm mass production. A new failure mechanism of metal 1 to poly (M1-to-poly) leaky path was proposed based on theoretical investigations and experiments. Based on our newly proposed dielectric breakdown mechanism, a series of innovative test structures were designed for early detections and evaluations of reliability performances. These newly designed test structures have been proven to be useful due to better representing actual using profiles, more precise reliability evaluations, and more effective monitors on process variations at mass production.

Three-Dimensional Nano-Acoustic Bragg Reflectors for CMOS Embedded NEMS

Integration of CMOS electronic circuits and electromechanical resonators has been pursued for a long time by many different research groups and even foundries. This would improve the overall performance of electromechanical oscillators and sensors. However, the postprocessing on the CMOS substrates that is necessary to attain this integration increases the production cost so much that it becomes not interesting in most cases. We present here a method of embedding a nano electromechanical resonator within a CMOS substrate by making use of the metal layers and intermetal dielectrics to build a phononic cage that stops most acoustic energy from being lost, and thus the resonator quality factor can reach values of more than 3000 at a frequency of 3.37 GHz, taking the particular case of a 65-nm node. Our results show that the performance of the integrated resonator, both in terms of quality factor and electromechanical coupling will improve when moving to smaller nodes, thus setting the roadmap for future hybrid systems.

The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process

Using low-k/ultralow-k (LK/ULK) materials as the inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials are fragile and the mechanical failures in ULK materials are critical during chip packaging processes, such as the solder reflow in the flip-chip. A crack or delamination that initiates within the high thermo-mechanical stress regions can propagate into the active area of the chip in packaging, which involves the chip-packaging interaction (CPI) problem. In this study, we proposed a three-dimensional sub-modeling finite element approach considering an effective layer for the back end of line (BEOL) microstructures in the global model to improve the accuracy. The approach surmounted the difficulty of the large size difference between the chip and the ULK layers in computations. The stress analysis and parametric studies for a designed ULK chip with 40nm technical node under the flip-chip reflow was performed based on the present method. The effects of the selected parameters were ranked and the optimal combination of the factors was achieved.

Effect of a Multi-Step Gap-Filling Process to Improve Adhesion between Low-K Films and Metal Patterns

A multi-step deposition process for the gap-filling of submicrometer trenches using dimethyldimethoxysilane (DMDMOS), (CH3)2Si(OCH3)2, and CxHyOz by plasma enhanced chemical vapor deposition (PECVD) is presented. The multistep process consisted of pre-treatment, deposition, and post-treatment in each deposition step. We obtained low-k films with superior gap-filling properties on the trench patterns without voids or delamination. The newly developed technique for the gapfilling of submicrometer features will have a great impact on inter metal dielectric (IMD) and shallow trench isolation (STI) processes for the next generation of microelectronic devices. Moreover, this bottom up gap-fill mode is expected to be universally for other chemical vapor deposition systems.

Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

The shrinking in feature sizes of semiconductor devices from integrated circuit (IC)11Integrated circuit (IC). and function complexity has led to greater PFA22Physical Failure Analysis (PFA). delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO2) material that is formed from Tetra Ethyl Ortho Silicate (TEOS)33Tetra Ethyl Ortho Silicate (TEOS). as Inter-Metal Dielectric (IMD)44Inter-Metal Dielectric (IMD). and very thin ultra low-k dielectric material.For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where die's side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset.This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.

Room Temperature Photoluminescence Characterization of Interface Quality of SiN/SiO2/Si Prepared under Various Deposition Techniques and Conditions

Various types of stacked dielectric films are used in complimentary metal-oxide-semiconductor (CMOS) devices in gates, capacitors and device isolation structures. They are also used as insulating materials between conductors, as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD). The preparation technique, structure and properties of dielectrics strongly influence the quality of the dielectrics/Si interface. Nominally, similar dielectrics/Si structures, even prepared by the same technique, often show different electrical properties depending on subtle differences in process conditions (hidden variables). Monitoring of physical dimensions and chemical compositions of dielectrics often miss unexpected variations in electrical properties. Non-contact electrical property characterization techniques lack lateral resolution and often results in impairment of the dielectrics/Si interface due to strong external electric fields from the measurement process. Alternative dielectrics/Si interface characterization techniques, which can provide insights into electrical properties without external electric field, would be very useful as a complimentary process and material quality monitoring technique. In this study, we have investigated the effect of SiN film deposition techniques on the interface quality of the resulting SiN/SiO2/Si using spectroscopic room temperature photoluminescence (RTPL) under multiwavelength excitation. The sample preparation procedures are as follows. First, ultra thin (~2.2 nm thick), gate oxide quality, thermal oxide films were grown on 300 mm Si(100) wafers. Nominally 5.0 nm thick SiN films were grown on ~2.0 nm thick SiO2/Si wafers using conventional low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) under various nitrogen source flow conditions. The film thickness was measured (after SiO2 film deposition) before and after SiN deposition using ellipsometry. Figure 1 (a) and (b) show RTPL spectra measured at the center of seven different SiN/SiO2/Si wafers under 650 nm excitation and showing maximum RTPL intensity under 650 nm and 827 nm excitation. Significantly large RTPL intensity variations were measured among the seven SiN/SiO2/Si wafers. The SiN film deposition conditions have modified the underlying SiO2/Si interface characteristics. Non-contact RTPL measurements are very sensitive to the thin film deposition techniques and conditions. It is effective as a complimentary dielectrics/Si process and interface characterization and monitoring technique. Figure 1

Development of chip shrink technology for lateral-type GaN based HFETs using SiO2/polyimide dual IMD layers

This study examined chip shrink technology for lateral-type AlGaN/GaN HFETs on 150 mm Si substrates fabricated with a bonding pad above the active area (BPAA) structure. The SiO2/polyimide layers were used as inter metal dielectric (IMD) layers, which yielded a very low leakage current of 0.58 nA/mm2 even at 1 kV and a good adhesion property after O2 plasma treatment. The fabricated AlGaN/GaN HFETs with the BPAA structure exhibited good device characteristics, such as a low leakage current of 7.1 nA at 1 kV and a drain current of 3.6 A at 2 V, which has the same value compared to that of the AlGaN/GaN HFETs without the BPAA structure, even though the BPAA structure reduced the size of chip by 40%. This suggests that the BPAA structure is a promising method for reducing the size and cost of the lateral-type AlGaN/GaN HFETs.

Dielectric Barrier, Etch Stop, and Metal Capping Materials for State of the Art and beyond Metal Interconnects

Over the past decade, the primary focus for improving the performance of nano-electronic metal interconnect structures has been to reduce the impact of resistance-capacitance (RC) delays via utilizing insulating dielectrics with ever lower values of dielectric permittivity. The integration and implementation of such low dielectric constant (i.e. low-k) materials has been fraught with numerous challenges. For intermetal and interlayer (ILD) low-k dielectrics, these challenges have been largely associated to integration with metal interconnect fabrication processes and well documented and reviewed in the literature. Although equally important, less attention has been given to other low-k dielectrics utilized in metal interconnect structures that are commonly referred to as low-k dielectric barriers (DB), etch stops (ES), and/or Cu capping layers (CCL). These materials present numerous challenges as well for integration into metal interconnect fabrication processes. However, they also have more stringent integrated functionality requirements relative to low-k ILD materials that serve only a basic purpose of electrically isolating adjacent metal lines. In this article, we review the integration challenges and associated integrated functionality requirements for low-k DB/ES/CCL materials with a focus on the current status and future direction needed for these materials to facilitate both Moore's law (i.e. More Moore) and More than Moore scaling.

Integration of Photodefinable Polybenzoxazole as Intermetal Dielectric for GaAs HBT Technology

Photodefinable polybenzoxazole (PBO) has been integrated as intermetal dielectric in GaAs hetero-junction bipolar transistor (HBT) technology. Process module optimization and integration studies were performed and the results and process flow were compared to those of dry-etch polyimide. The photodefinable PBO is shown to allow the intermetal dielectric process flow to be simplified and the number of processes and equipment to be reduced. Results show that PBO has more planarity than polyimide, when coated on GaAs HBT wafers, which typically have significant topography. The photolithography coat, expose, and develop processes were optimized to obtain the desired dielectric thickness and the required via dimension and sidewall profile, in addition the removal of the PBO from the die street. The PBO thermal curing process was performed at 300oC, while plasma ashing was performed to remove any PBO residue from the bottom of the vias. These results show that the photodefinable PBO film is compatible with, is suitable for, and can be integrated as intermetal dielectric in GaAs HBT technology.

Integration of Photodefinable Polybenzoxazole as Intermetal Dielectric for GaAs HBT Technology

Polybenzoxazole (PBO) is a polymer dielectric that has excellent mechanical, physical, and electrical characteristics and that is used for various semiconductor thin film applications. The PBO has low dielectric constant, and has good thermal stability and thermo-oxidative resistance. Furthermore, the PBO material can be applied by spin-coating and can be cured at temperature of <300oC, which is significantly lower than many other spin-on dielectric materials. These characteristics make PBO suitable for use in many semiconductor technologies and applications that require the processing temperatures not to exceed 300oC, such as GaAs hetero-junction bipolar transistor (HBT) technology. The PBO material is easily processed, and can be made photodefinable by adding photoactive compounds, and therefore be patterned on semiconductor wafers. By using a photodefinable PBO dielectric material, there will not be any need to perform patterning by dry-etch process steps that are typically performed in GaAs technologies.In this study, photodefinable PBO has been integrated as intermetal dielectric in GaAs HBT technology. Process module optimization and integration studies were performed and the PBO results and process flow were compared to those of dry-etch polyimide, which is typically used as intermetal dielectric in GaAs technology. The photodefinable PBO is shown to allow the intermetal dielectric process flow to be simplified and the number of processes and equipments to be reduced. Results show that PBO has more planarity than polyimide, when coated on GaAs HBT wafers, which typically have significant topography. The PBO photolithography coat, expose, and develop processes were optimized in order to obtain the desired dielectric thickness and the required via dimension and sidewall profile, in addition to removing the PBO from the die street. The PBO thermal curing process was performed at 300oC, while ashing was performed to remove any PBO residue in the vias and streets. Figure 1 shows the FIB/SEM images of GaAs wafer after deposition of Metal 1 and coated with photodefinable, after via expose and develop, after cure, and after ash. Figure 2 shows the GaAs HBT wafer with (a) dry-etch polyimide and (b) photodefinable PBO used as intermetal dielectric. These results show that the photodefinable PBO film is compatible with, is suitable for, and can be integrated as intermetal dielectric in GaAs HBT technology.

Predict VLSI Circuit Reliability Risks Using Neural Network

This paper describes the challenges faced in predicting the reliability of very large scale integration (VLSI) circuits. Currently, lots of trial-and-errors are still needed for the parameters selected to develop a neural network prediction model, whose result is with a great deal of uncertainty. The objective of this paper is to provide a novel and practical approach to design a reliability prediction model using neural network. We propose a seven-step procedure to formulate an optimal neural network design and explain it in details using a case study on semiconductor reliability. We combine reliability test characteristics (e.g., early failures) with statistical methods such as regression and design of experiment (DOE) for this optimal neural network model and get comparably small prediction errors. Following our proposed approach, analysts can develop effective designs with higher prediction accuracy. We further introduce an operation flow to maximize the benefits from the obtained optimal prediction model by earlier nonconformance detection and faster lot dispositions, which are reported in the case study on successfully implementing our methodology to predict inter metal dielectric (IMD) reliability risks. Our proposed approach can be easily applied on many other fields like yield prediction.

Thermal effect of Ge2Sb2Te5 in phase change memory device

In the fabrication of phase change random access memory (PRAM) devices, high temperature thermal processes are inevitable. We investigate the thermal stability of Ge2Sb2Te5 (GST) which is a prototypical phase change material. After high temperature process, voids of phase change material exist at the interface between Ge2Sb2Te5 and substrate in the initial open memory cell. This lower region of Ge2Sb2Te5 is found to be a Te-rich phase change layer. Phase change memory devices are fabricated in different process conditions and examined by scanning electron microscopy and energy dispersive X-ray. It is found that hot-chuck process, nitrogen-doping process, and lower temperature inter-metal dielectric (IMD) deposition process can ease the thermal impact of line-GST PRAM cell.

Oxide Impurities in Silicon Oxide Intermetal Dielectrics and Their Potential to Elevate Via-Resistances

Silicon oxide used as an intermetal dielectric (IMD) incorporates oxide impurities during both its formation and subsequent processing to create vias in the IMD. Without a sufficient degassing of the IMD, oxide impurities released from the IMD during the physical vapor deposition (PVD) of the glue layer of the vias had led to an oxidation of the glue layer and eventual increase of the via resistances, which correlated with the O-to-Si atomic ratio of the IMD being ~10% excessive as verified by transmission electron microscopy (TEM) analysis. A vacuum bake of the IMD was subsequently implemented to enhance outgassing of the oxide impurities in the IMD before the glue layer deposition. The implementation successfully reduced the via resistances to an acceptable level.

Highly transparent silica aerogel thick films with hierarchical porosity from water glass via ambient pressure drying

Highly transparent silica aerogel films of 2–3.6 μm thick and with the hierarchical porosity were deposited on fluorine doped tin oxide (FTO) conductive glass substrate via the sol–gel and ambient drying processes, by using water glass as the silicic source. An innovative aging process was developed by immersing the hydrogel film in large volume of tetraethoxysilane (TEOS)–ethanol solution. Obtained aerogel films possessed both the mesopores and the submicron pores, with the average pore size of 19.1 nm, the specific surface area of 530 m2 g−1, and the pore volume of 2.96 cm3 g−1. The leaching of silicic acid molecules from the hydrogel film into the bulk aging solution was responsible for the formation of submicron pores. The aging of the hydrogel film in TEOS–ethanol solution could greatly enhance the silica skeleton and resist the film shrinkage during the ambient drying process, and an aging time longer than 8 h was appropriate to obtain thick aerogel films without obvious structure collapse. The SiO2 content in the precursor should be kept at medium level, to avoid nonuniform film thickness or lower surface area. In addition, the aerogel film synthesized at optimal condition possessed good hydrophobicity (contact angle: 132°), high transparency (70–82% in 400–1200 nm band), and low dielectric constant (k = 1.42). The work demonstrates a facile and low-cost route toward transparent silica aerogel films with hierarchical pore structures, which can be used as the intermetal dielectrics or the template to synthesize novel functional materials requiring high transmittance, high surface area and effective mass transport.

THE TEST-TO-TARGET METHODOLOGIES FOR THE RISK ASSESSMENT OF SEMICONDUCTOR RELIABILITY

Traditionally, to assess reliability lifetimes and to evaluate reliability performance of semiconductor devices and chips, we test the samples to their failures. This can be called the "Test-to-Fail" scenario, which usually takes a long time (e.g., longer than a week). The Test-to-Failure scenario is required especially at the qualification stage, whose objective is to obtain the lifetimes of, e.g., devices, dielectrics, and metal lines. Due to the long test times, this approach is inadequate for reliability monitors, which need to be completed in a much shorter period of time so the product shipment will not be delayed and, if failed, timely corrective actions can be taken. Therefore, we are in urgent need of a much more efficient method to judge if the monitor meets reliability requirements. The "Test-to-Target" reliability test methodology perfectly matches such demand by only stressing the samples to much shorter times and can be applied on most common reliability tests like NBTI (Negative Bias Temperature Instabilities), HCI (Hot Carrier Injection), TDDB (Time Dependent Dielectric Breakdown), Isothermal EM test, and IMD (Inter Metal Dielectric) Vramp test. The corresponding specs for the Test-to-Target approach are defined based on the baseline records from the former complete Test-to-Fail reliability tests. From practical exercises after a long time, we prove the Test-to-Target methodology a truly useful approach particularly effective for reliability monitors, inline reliability assessments, process change management, nonconformance dispositions, and tool releases.

Prevention of plasma-induced damage on thin gate oxides in BEOL sub-half micron CMOS processing

A comparison is made of several plasma-induced damage (PID) measurement techniques. A novel PID mechanism using high-density plasma (HDP) inter-metal dielectric (IMD) deposition is proposed. The results of a design of experiment (DOE) on Ar pre-clean minimizing PID are presented. For HDP oxide deposition, the plasma damage is minimal, assuring minimal exposure time of the metal line to the plasma using a maximal deposition to sputter ratio. This process induces less PID than classic SOG processing. Ar pre-clean induces minimal plasma damage using minimal process time, high ion energy and high plasma power. For metal etching, an HDP etch is compared to a reactive ion etch, and the impact of the individual process steps are identified by specialized antenna structures. The measurement results of charge pumping, breakdown voltage and gate oxide leakage correlate very well. On metal etching, the reactive ion etching induces less plasma damage than HDP etching. For both reactors, PID is induced only in the metal over-etch step.

Synthesis and characterisation of gold nanoparticle doped ceria-rice husk silica nanocomposites derived from biomass

To realise high performance in IC devices, it is necessary to reduce the RC delay, cross talk, and power consumption. An effective method to make these reductions is to decrease the parasitic capacitance by employing a low dielectric constant (low-k) material in the intermetal dielectrics (IMD). The present research topic deals with the synthesis and characterisation of gold doped in ceria-silica, derived from rice husk biomass materials. Large amount of silica recovered from waste rice husk silica, hence the silica materials derived from waste product can be the low cost and used for potential application such as low-k dielectric material development. Gold doping on ceria-mixed silica derived from rice husk is carried out by insitu method (Au/Ce-silica-A) and deposition-co precipitation method (Au/Ce-silica-B). Au/Ce-silica-A and Au/Ce-silica-B shown the low-k dielectric constant compared to bulk ceria-silica.

Virtual Metrology Modeling for CVD Film Thickness

The semiconductor industry is continuously facing four main challenges in film characterization techniques: accuracy, speed, throughput and flexibility. Virtual Metrology (VM), defined as the prediction of metrology variables using process and wafer state information, is able to successfully address these four challenges. VM is understood as definition and application of predictive and corrective mathematical models to specify metrology outputs (physical measurements). These statistical models are based on metrology data and equipment parameters. The objective of this study is to develop a model predicting the CVD oxide thickness (average) for an IMD (Inter Metal Dielectric) deposition process using FDC data (Fault Detection and Classification) and metrology data. In this paper, two VM models are studied: one based on Partial Least Squares Regression (PLS) and one based on Tree ensembles. We will demonstrate that both models show good predictive strength. Finally, we will highlight that model update is key for ensuring a good model robustness over time and that an indicator of confidence of the predicted values is necessary too if the VM model has to be use on-line in a production envi- ronment.

Combining neural networks and genetic algorithms for optimising the parameter design of the inter-metal dielectric process

An inter-metal dielectric (IMD) is deposited between metal layers to provide isolation capability to a device and separate the different metal layers that are unnecessary in the conduction of electricity. Owing to the complicated input/response relationships of the IMD process, the void problem results in electric leakage and causes wafer scraping. In the current study, we combined neural networks, genetic algorithms (GAs) and the desirability function in order to optimise the parameter settings of the IMD process. Initially, a backpropagation (BP) neural network was developed to map the complex non-linear relationship between the process parameters and the corresponding responses. Moreover, the desirability function and GAs were employed to obtain the optimum operating parameters in respect to each response. The implementation of the proposed approach was carried out in a semiconductor manufacturing company in Taiwan, and the results illustrate the practicability of the proposed approach.

Reducing Metal-Lifting Defect during Wire Bonding through Device Structure and Process Optimization

This article focuses on the methods of reducing Lifted Metal (LM) defects by optimizing the semiconductor manufacturing process. The LM defect was found to be associated with the insufficient adhesion between metal layers and Inter Metal Dielectric (IMD) together with cracking IMD layers. 5 feasible methods are applied to decrease LM defects. The wire bonding test results show that the incorporation of Tetraethoxysilane (TEOS) layer between Nitrogen Doped Carbide (NDC) and Black Diamond (BD) proves the most useful to decrease Au wire bonding LM defect to 1/39.8 and Cu wire bonding LM defect to 1/9.25. This method to reduce LM defects has passed all the wafer qualification tests, thus it is being used in IC mass production.